IP Library › Granted Patent US 7,864,192
Granted Patent B2
US 7,864,192 · App. 11/946,225 · Granted Jan 4, 2011

Dithering system and method for use in image processing

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,864,192
App. No.
11/946,225
Granted
Jan 4, 2011
Kind
B2
Abstract

A dithering system includes a linear transformer, a dither data generator, an adder and a shifter. The transformer linearly transforms M bit input data using a linear function having a predetermined gradient in order to generate and output M bit transform data. The dither data generator generates and outputs M−N bit dither data. The adder adds the M bit transform data and the M−N bit dither data to generate and output M bit correction data. The shifter cuts off the bottom M−N bits of the M bit correction data in order to generate and output the N bit output data. The dithering system and associated dithering method widely disperses an error generated due to a physical limit of a data bit that can be expressed by a low gray scale system throughout the entirety of the gray scales when high gray scale image data is converted to low gray scale image data. This is done without using a lookup table which avoids using valuable chip area. In addition, by utilizing a plurality of adders and shifters rather than a multiplier and divider, the number of required logic gates is remarkably reduced as well as reducing associated power requirements.

Claims (168)

1. A dithering system utilized in image processing, the dithering system comprising:

a linear transformer which linearly transforms received M bit input data using a linear function having a predetermined gradient to generate and output M bit transform data where M is a natural number;

a dither data generator configured to generate and outputs M−N bit dither data where N is a natural number and N<M;

an adder connected to the linear transformer and the dither data generator, the adder configured to add the M bit transform data from the linear transformer and the M−N bit dither data from the dither data generator to generate and output M bit correction data; and

a shifter connected to the adder and configured to cut-off the bottom M−N bits of the M bit correction data received from the adder to generate and output N bit output data.

2. The dithering system of claim 1 wherein the gradient of the linear function is

2

M

-

1

-

(

2

M

-

N

-

1

)

+

α

OFFSET

2

M

-

1

+

β

OFFSET

where αOFFSET is a first variable and βOFFSET is a second variable.

3. The dithering system of claim 2 wherein the linear function has a y intercept equal to the gradient of the linear function.

4. The dithering system of claim 2 wherein a numerator a of the slope of the linear function is converted to satisfy

α

=

∑

i

=

0

M

-

1

⁢

C

i

×

2

i

,

C

optimum

⁢

⁢

set

=

arg

⁢

⁢

min

⁢

∑

C

i

.

5. The dithering system of claim 4 wherein βOFFSET is 1.

6. The dithering system of claim 5 wherein the linear transformer is formed only of a plurality of adders in combination with a plurality of shifters.

7. The dithering system of claim 6 wherein the shifter is a barrel shifter.

8. The dithering system of claim 1 further comprising an over-sampling unit connected to the linear transformer is configured to over-sample the M bit input data to generate 2(M−N) identical strings of each M bit input data string and output the M−N identical strings to the linear transformer.

9. The dithering system of claim 1 wherein the linear transformer performs a fixed point calculation.

10. The dithering system of claim 1 wherein the N output data is supplied to a liquid crystal display.

11. A dithering system utilized in image processing which converts received M bit input data to N bit output data where M and N are natural numbers and N<M, the dithering system comprising:

a dither data generator configured to generate and output M−N bit dither data;

an adder connected to the dither data generator configured to add the M bit input data and the M−N bit dither data received from the dither data generator to generate and output M bit correction data;

a linear transformer connected to the adder and receiving the output M bit correction data, the linear transformer configured to linearly transform the M bit correction data using a linear function in a predetermined slope to generate and output M bit transform data; and

a shifter connected to the linear transformer and configured to cut-off the bottom M−N bits of the M bit transform data to generate and output the N bit output data.

12. The dithering system of claim 11 wherein the gradient of the linear function is

2

M

-

1

-

(

2

M

-

N

-

1

)

+

α

OFFSET

2

M

-

1

+

(

2

M

-

N

-

1

)

⁢

β

OFFSET

where αOFFSET is a first variable and βOFFSET is a second variable.

13. The dithering system of claim 12 wherein a numerator a of the gradient of the linear function is converted to satisfy

α

=

∑

i

=

0

M

-

1

⁢

C

i

×

2

i

,

C

optimum

⁢

⁢

set

=

arg

⁢

⁢

min

⁢

∑

C

i

.

14. The dithering system of claim 13 wherein βOFFSET is 2−2M−N.

15. The dithering system of claim 11 further comprising an over-sampling unit connected to the adder is configured to over-sample the M bit input data to generate 2(M−N) identical strings of each M bit input data string and output the M−N identical strings to the adder.

16. The dithering system of claim 11 wherein M is 8 and N is 6.

17. The dithering system of claim 11 wherein the dither data generator sequentially generates and outputs M−N bit dither data having different logic levels.

18. A dithering method utilized in image processing which converts M bit input data to N bit output data using dither data wherein M and N are natural numbers and N<M, the dithering method comprising:

linearly transforming the M bit input data to M bit transform data using a linear function having a predetermined gradient;

outputting the M bit transform data;

generating and outputting M−N bit dither data;

adding the M bit transform data and the M−N bit dither data to generate and output M bit correction data; and

generating and outputting the N bit output data by cutting off the bottom M−N bits of the M bit correction data.

19. The dithering method of claim 18 further comprising:

generating 2(M−N) identical strings of each M bit input data string by over-sampling the M bit input data; and

outputting the 2(M−N) identical strings to undergo the linear transformation of the M−N pieces of M bit input data to M−N pieces of M bit transform data.

20. The dithering method of claim 18 further comprising supplying the N bit output data to a liquid crystal display.

21. A dithering method utilized in image processing which converts M bit input data to N bit output data using dither data wherein M and N are natural numbers and N<M, the dithering method comprising:

generating and outputting M−N bit dither data;

generating and outputting M bit correction data by adding the M bit input data and the M−N bit dither data;

linearly transforming the M bit correction data to M bit transform data using a linear function having a predetermined gradient;

outputting the M bit transform data; and

generating and outputting the N bit output data by cutting off the bottom M−N bits of the M bit transform data.

22. The dithering method of claim 21 , further comprising:

generating 2(M−N) identical strings of each M bit input data string by over-sampling the M bit input data;

outputting the 2(M−N) identical strings of each M bit input data wherein the M bit correction data and the M−N strings of M bit correction data are generated and output by adding the over sampled 2(M−N) identical strings of each M bit input data string and a corresponding plurality of portions of M−N bit dither data.

23. The dithering method of claim 21 wherein a plurality of portions of M−N bit dither data having different logic levels is sequentially generated and outputted.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2007
From: KIM, CHANG-MIN; LEE, JAE-CHUL; KIM, JONG-SEON
To: SAMSUNG ELECTRONICS CO.,LTD.
Reel/Frame 020179/0491 →
Priority Claims (1)
KR 10-2007-0026255 · Mar 16, 2007 · national
Continuity (1)
Related Publication 20080225054A1 · Sep 18, 2008