Programmable clock control architecture for at-speed testing
According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The N-stage programmable clock control architecture further includes means for programming the N flip-flops such that the N-stage programmable clock control architecture outputs N programmed at-speed clock pulses. For example, when N is equal to 3, three programmed clock pulses can be outputted by the N-stage programmable clock control architecture, with a total of eight different patterns of programmed clock pulses. The N-stage programmable clock control architecture can thus adequately test, for example, combinational logic requiring greater than two consecutive clock pulses for complete at-speed testing. In one embodiment, scan-shift registers can be utilized to program the N flip-flops. In another embodiment, a look-up table can be used to program the N flip-flops.
1. An N-stage programmable clock control architecture, comprising:
N flip-flops, said N flip-flops being clocked by a primary clock source;
means for programming said N flip-flops such that said N-stage programmable clock control architecture outputs at least two programmed at-speed clock pulses;
said means performing a logical operation on a clock signal from said primary clock source and a last flip-flop, said last flip-flop coupled to said N flip-flops.
2. The N-stage programmable clock control architecture of claim 1 , wherein said means for programming said N flip-flops comprises scan-shift registers.
3. The N-stage programmable clock control architecture of claim 1 , wherein said means for programming said N flip-flops comprises a look-up table.
4. The N-stage programmable clock control architecture of claim 1 , wherein said N-stage programmable clock control architecture produces 2 N patterns of said programmed at-speed clock pulses.
5. The N-stage programmable clock control architecture of claim 1 , wherein said N-stage programmable clock control architecture outputs N at-speed clock pulses.
6. The N-stage programmable clock control architecture of claim 1 , wherein said N-stage programmable clock control architecture is implemented on-chip.
7. The N-stage programmable clock control architecture of claim 1 , wherein said primary clock source is a PLL.
8. The N-stage programmable clock control architecture of claim 1 , wherein said primary clock source has a frequency between approximately 200MHz and approximately 1 GHz.
9. The N-stage programmable clock control architecture of claim 1 , wherein said N-stage programmable clock control architecture outputs at least one programmed dead clock cycle.
10. An N-stage programmable clock control architecture, comprising:
a chain of N flip-flops, said chain of N flip-flops being clocked by a primary clock source;
means for programming said chain of N flip-flops such that said N-stage programmable clock control architecture outputs N at-speed clock pulses synchronized with said primary clock source;
said means performing a logical operation on a clock signal from said primary clock source and a last flip-flop, said last flip-flop coupled to said chain of N flip-flops.
11. The N-stage programmable clock control architecture of claim 10 , wherein said means for programming said chain of N flip-flops comprises scan-shift registers.
12. The N-stage programmable clock control architecture of claim 10 , wherein said means for programming said chain of N flip-flops comprises a look-up table.
13. The N-stage programmable clock control architecture of claim 10 , wherein said N-stage programmable clock control architecture produces 2 N patterns of said programmed at-speed clock pulses.
14. The N-stage programmable clock control architecture of claim 10 , wherein said N-stage programmable clock control architecture outputs at least two at-speed clock pulses.
15. The N-stage programmable clock control architecture of claim 10 , wherein said N-stage programmable clock control architecture outputs at least three at-speed clock pulses.
16. The N-stage programmable clock control architecture of claim 10 , wherein said N-stage programmable clock control architecture is implemented on-chip.
17. The N-stage programmable clock control architecture of claim 10 , wherein said primary clock source has a frequency between approximately 200 MHz and approximately 1 GHz.
18. The N-stage programmable clock control architecture of claim 10 , wherein said N-stage programmable clock control architecture outputs at least one programmed dead clock cycle.
19. The N-stage programmable clock control architecture of claim 10 , wherein said primary clock source is a PLL.