IP Library › Granted Patent US 7,865,823
Granted Patent B2
US 7,865,823 · App. 11/823,590 · Granted Jan 4, 2011

Method and apparatus for schema validation

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,865,823
App. No.
11/823,590
Granted
Jan 4, 2011
Kind
B2
Abstract

In one embodiment, the invention may include receiving an XML schema and document with first, second, third, and fourth nodes. The second and third nodes may descend from the first node. The fourth node may descend from the second node. The third and fourth nodes may be simultaneously validated.

Claims (39)

1. A method comprising:

receiving an XML schema;

receiving a parsed XML document that includes a parent node, a first child node, a second child node, and a grandchild node;

validating the first child node; and

simultaneously validating the second child node and the grandchild node;

wherein the first child node directly descends from the parent node, the second child node directly descends from the parent node, and the grandchild node directly descends from the first child node.

2. The method of claim 1 , further comprising:

validating the second child node with a first processor core; and

validating the grandchild node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

3. The method of claim 1 , further comprising validating the second child node via a first thread and validating the grandchild node via a second thread, the first thread and the second thread validated using a single core processor.

4. The method of claim 1 , further comprising:

validating the second child node via a first finite state machine; and

validating the grandchild node via a second finite state machine.

5. The method of claim 4 , further comprising validating the parent node via a host finite state machine, the host finite state machine including the first finite state machine and the second finite state machine.

6. The method of claim 1 , further comprising:

validating the first child node with a first processor core; and

validating the second child node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

7. The method of claim 1 , further comprising completing validation of the second child node after completing validation of the grandchild node.

8. An article comprising a medium storing instructions that enable a processor-based system to:

receive an XML schema;

receive a parsed XML document that includes a parent node, a first child node, a second child node, and a grandchild node;

validate the first child node; and

simultaneously validate the second child node and the grandchild node;

wherein the first child node descends from the parent node, the second child node descends from the parent node, and the grandchild node descends from the first child node.

9. The article of claim 8 storing instructions that enable the system to:

validate the second child node with a first processor core; and

validate the grandchild node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

10. The article of claim 8 storing instructions that enable the system to validate the second child node via a first thread and validate the grandchild node via a second thread, the first thread and the second thread to be validated using a single core processor.

11. The article of claim 8 storing instructions that enable the system to: validate the second child node via a first finite state machine; and

validate the grandchild node via a second finite state machine.

12. The article of claim 11 storing instructions that enable the system to validate the parent node via a host finite state machine, the host finite state machine including the first finite state machine and the second finite state machine.

13. The article of claim 8 storing instructions that enable the system to:

validate the first child node with a first processor core; and

validate the second child node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

14. The article of claim 8 storing instructions that enable the system to complete validation of the second child node after completing validation of the grandchild node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2010
From: MATHESON, JACK; TSOI, HOWARD
To: INTEL CORPORATION
Reel/Frame 024936/0992 →
Continuity (1)
Related Publication 20090006943A1 · Jan 1, 2009