Solving via-misalignment issues in interconnect structures having air-gaps
View Patent ↗An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer.
1. An integrated circuit structure comprising:
a semiconductor substrate;
a metallization layer over the semiconductor substrate, wherein the metallization layer comprises:
a conductive line;
a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and
a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials;
an air-gap within and enclosed by the filler dielectric material; and
a capping layer over and adjoining the filler dielectric material and the low-k dielectric region, wherein the filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer.
2. The integrated circuit structure of claim 1 , wherein the filler dielectric material further comprises a portion vertically between and adjoining the air-gap and the capping layer.
3. The integrated circuit structure of claim 1 , wherein the air-gap adjoins the capping layer.
4. The integrated circuit structure of claim 1 , wherein the filler dielectric material has a portion extending over the low-k dielectric region and vertically spacing the low-k dielectric region apart from the capping layer.
5. The integrated circuit structure of claim 1 further comprising an etch stop layer having a bottom level with a bottom of the conductive line, wherein a top surface of the etch stop layer adjoins the low-k dielectric region and the filler dielectric material.
6. The integrated circuit structure of claim 1 further comprising a sidewall protection layer adjoining a sidewall of the conductive line, wherein the sidewall protection layer adjoins the filler dielectric material.
7. The integrated circuit structure of claim 1 , wherein the filler dielectric material has a top width and a bottom width, and wherein the top width is greater than the bottom width.
8. An integrated circuit structure comprising:
a semiconductor substrate;
a low-k dielectric layer over the semiconductor substrate;
a conductive line in the low-k dielectric layer;
a filler dielectric material horizontally between the low-k dielectric layer and the conductive line, wherein the filler dielectric material adjoins the low-k dielectric layer, and wherein the filler dielectric material and the low-k dielectric layer have different k values;
a capping layer over and adjoining the filler dielectric material and the low-k dielectric layer, wherein the filler dielectric material has a k value lower than a k value of the capping layer; and
an air-gap encircled by the filler dielectric material, wherein the air-gap is within and enclosed by the filler dielectric material, with a portion of the filler dielectric material directly over the air-gap and separating the air-gap from the capping layer.
9. The integrated circuit structure of claim 8 , wherein the filler dielectric material has a bottom surface level with a bottom surface of the low-k dielectric layer.
10. The integrated circuit structure of claim 8 , wherein the conductive line comprises a diffusion barrier layer, and a copper line in an inner region formed by the diffusion barrier layer.
11. The integrated circuit structure of claim 8 further comprising a sidewall protection layer adjoining a sidewall of the conductive line, wherein the sidewall protection layer further adjoins the filler dielectric material.
12. The integrated circuit structure of claim 8 , wherein the filler dielectric material has a top width and a bottom width, and wherein the top width is greater than the bottom width.
13. An integrated circuit structure comprising:
a semiconductor substrate;
an etch stop layer (ESL) over the semiconductor substrate;
a low-k dielectric layer over and adjoining the etch stop layer; and
a filler material over the etch stop layer and adjoining the etch stop layer and the low-k dielectric layer, wherein an air-gap is within and enclosed by the filler material, and wherein the filler material and the low-k dielectric layer comprise different dielectric materials.
14. The integrated circuit structure of claim 13 further comprising a metal line in the ESL and the low-k dielectric layer, wherein the filler material adjoins a sidewall of the metal line.
15. The integrated circuit structure of claim 13 further comprising:
a metal line in the ESL and the low-k dielectric layer; and
a sidewall protection layer on a sidewall of the metal line, wherein a bottom edge of the sidewall protection layer is level with a bottom surface of the metal line, and wherein the filler material adjoins a sidewall of the sidewall protection layer.
16. The integrated circuit structure of claim 13 , wherein the filler material comprises a top portion having a first width over a bottom portion having a second width, wherein the first width is greater than the second width.