Semiconductor memory device and method for repairing the same

1. A semiconductor memory device comprising:

a main cell array region including main bitlines;

a first redundancy cell array region including a first redundancy bitline and a first dummy cell array region including first dummy bitlines, the first redundancy cell array region and the first dummy cell array region being formed at one side of the main cell array region; and

a second redundancy cell array region including a second redundancy bitline and a second dummy cell array region including second dummy bitlines, the second redundancy cell array region and the second dummy cell array region being formed at the other side of the main cell array region,

wherein the first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.

2. The semiconductor memory device of claim 1 , further comprising:

a third redundancy cell array region including a third redundancy bitline and a third dummy cell array region including third dummy bitlines, the third redundancy cell array region and the third dummy cell array region being formed at the one side of the main cell array region; and

a fourth redundancy cell array region including a fourth redundancy bitline and a fourth dummy cell array region including fourth dummy bitlines, the fourth redundancy cell array region and the fourth dummy cell array region being formed at the other side of the main cell array region,

wherein the third and fourth redundancy cell array regions are disposed closer to the main cell array region than the third and fourth dummy cell array regions.

3. The semiconductor memory device of claim 2 , wherein the first redundancy cell array region is disposed closer to the main cell array region than the third redundancy cell array region; and

the second redundancy cell array region is disposed closer to the main cell array region than the fourth redundancy cell array region.

4. The semiconductor memory device of claim 3 , wherein the first dummy cell array region is disposed closer to the main cell array region than the third redundancy cell array region; and

the second dummy cell array region is disposed closer to the main cell array region than the fourth redundancy cell array region.

5. The semiconductor memory device of claim 4 , wherein the number of the third dummy bitlines is larger than the number of the first dummy bitlines, and the number of the fourth dummy bitlines is larger than the number of the second dummy bitlines.

6. The semiconductor memory device of claim 2 , wherein the main cell array region includes local bitlines that are respectively connected to the main bitlines; and

the first to fourth redundancy cell array regions include local redundancy bitlines that are respectively connected to the first to fourth redundancy bitlines.

7. The semiconductor memory device of claim 1 , further comprising:

a third redundancy cell array region including a third redundancy bitline, the third redundancy cell array region being formed between the first redundancy cell array region and the first dummy cell array region; and

a fourth redundancy cell array region including a fourth redundancy bitline, the fourth redundancy cell array region being formed between the second redundancy cell array region and the second dummy cell array region.

8. The semiconductor memory device of claim 1 , wherein the first redundancy cell array region and the second redundancy cell array region are directly adjacent to the main cell array region.

9. A method for repairing a semiconductor memory device including a main cell array region and a plurality of redundancy cell array regions, the method comprising:

determining whether there is a fail cell in the main cell array region of the semiconductor memory device;

selecting a redundancy bitline of one of the redundancy cell array regions to replace a main bitline electrically connected to a determined fail cell, the selecting being based on proximity of the redundancy cell array regions to the main cell array region of the semiconductor memory device; and

replacing the main bitline electrically connected to the determined fail cell with the selected redundancy bitline, wherein

the plurality of redundancy cell array regions include

a first redundancy cell array region having a first redundancy bitline and a third redundancy cell array region having a third redundancy bitline, the first redundancy cell array region and the third redundancy cell array region being formed one side of the main cell array region, and

a second redundancy cell array region having a second redundancy bitline and a fourth redundancy cell array region havinj a fourth redundancy bitline, the second redundancy cell array region and the fourth redundancy cell array region being formed at the other side of the main cell array region, and

the first and second redundancy cell array regions are disposed to be closer to the main cell array region than the third and fourth redundancy cell array regions.

10. The method of claim 9 , wherein the selecting selects the redundancy bitline from an available redundancy cell array region in closest proximity to the main cell array region.

11. The method of claim 9 , further comprising:

a first dummy cell array region including first dummy bitlines disposed between the first redundancy cell array region and the third redundancy cell array region; and

a second dummy cell array region including second dummy bitlines disposed between the second redundancy cell array region and the fourth redundancy cell array region.

12. The method of claim 9 , wherein,

a distance between the first redundancy bitline and the main cell array region is equal to a distance between the second redundancy bitline and the main cell array region, and a distance between the third redundancy bitline and the main cell array region is equal to a distance between the fourth redundancy bitline and the main cell array region; and

the replacing the main bitline electrically connected to the determined fail cell with the selected redundancy bitline includes selecting a redundancy bitline to replace the main bitline in the order of the first redundancy bitline, the second redundancy bitline, the third redundancy bitline, and the fourth redundancy bitline.