Memory controller prioritization scheme
A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.
1. A memory controller comprising:
a first queue configured to store memory requests;
a second queue configured to store memory requests received from the first queue; and
control logic configured to assign a priority to each memory request stored in the first queue;
wherein the control logic is configured to:
assign a priority to each memory request stored in the first queue;
select a given memory request in the first queue for conveyance to the second queue, wherein the given memory request is selected based at least in part on an assigned priority; and
change a priority of at least one memory request stored in the first queue and at least one memory request stored in the second queue, in response to detecting a trigger.
2. The memory controller of claim 1 , wherein in response to detecting the trigger corresponds to a given request type, the control logic is configured to change a priority of each memory request stored in each of the first queue and the second queue corresponding to the given request type.
3. The memory controller of claim 1 , wherein the memory controller is further configured to maintain an entry in the first queue for a given memory request that is sent to the second queue until the given memory request is processed out of the second queue.
4. The memory controller of claim 1 , wherein at least one stored memory request is a write request, the trigger comprises detecting that a number of write requests stored in the first queue is greater than or equal to a threshold value, and the memory controller is configured to increase a priority of each write request stored in the first queue and the second queue responsive to the trigger.
5. The memory controller of claim 4 , wherein the threshold value is programmable.
6. The memory controller of claim 1 , wherein at least one stored memory request is an isochronous memory request, the trigger comprises detecting that at least one isochronous memory request has been pending in the first queue for at least a predetermined time period, and the memory controller is configured to increase a priority of each isochronous memory request stored in the first queue and the second queue responsive to the trigger.
7. The memory controller of claim 6 , wherein the predetermined time period is programmable.
8. The memory controller of claim 1 , wherein at least one stored memory request is a prefetch request, the trigger comprises detecting a demand read request whose address matches an address of a stored prefetch request, and the memory controller is configured to increase a priority of each stored prefetch request in the first queue and the second queue whose address matches the address of the demand read request responsive to the trigger.
9. A system comprising:
a processor;
a memory coupled to the processor; and
a memory controller comprising a first queue and a second queue, wherein the memory controller is configured to:
store each received memory request from the processor in the first queue;
assign a priority to received memory request stored in the first queue;
select a given memory request in the first queue for conveyance to the second queue, wherein the given memory request is selected based at least in part on an assigned priority; and
change a priority of at least one memory request stored in the first queue and at least one memory request stored in the second queue, in response to detecting a trigger.
10. The system of claim 9 , wherein in response to detecting a trigger corresponds to a given request type, the control logic is configured to change a priority of each memory request stored in each of the first queue and the second queue corresponding to the given request type.
11. The system of claim 9 , wherein the memory controller is further configured to maintain an entry in the first queue for a given memory request that is sent to the second queue until the given memory request is processed out of the second queue.
12. The system of claim 9 , wherein at least one stored memory request is a write request, the trigger comprises detecting that a number of write requests stored in the first queue is greater than or equal to a threshold value, and the memory controller is configured to increase a priority of each write request stored in the first queue and the second queue responsive to the trigger.
13. The system of claim 9 , wherein at least one stored memory request is an isochronous memory request, the trigger comprises detecting that at least one isochronous memory request has been pending in the first queue for at least a predetermined time period, and the memory controller is configured to increase a priority of each isochronous memory request stored in the first queue and the second queue responsive to the trigger.
14. The system of claim 9 , wherein at least one stored memory request is a prefetch request, the trigger comprises detecting a demand read request whose address matches an address of a stored prefetch request, and the memory controller is configured to increase a priority of each stored prefetch request in the first queue and the second queue whose address matches the address of the demand read request responsive to the trigger.
15. A method comprising:
receiving memory requests;
storing each received memory request in a first queue;
assigning a priority to each memory request stored in the first queue;
selecting a given memory request in the first queue for conveyance to a second queue, wherein the given memory request is selected based at least in part on an assigned priority; and
changing a priority of at least one memory request stored in the first queue and at least one memory request stored in the second queue, in response to detecting a trigger.
16. The method of claim 15 , wherein in response to detecting the trigger corresponds to a given request type, changing a priority of each memory request stored in each of the first queue and the second queue corresponding to given request type.
17. The method of claim 15 , further comprising maintaining an entry in the first queue for a given memory request that is sent to the second queue until the given memory request is processed out of the second queue.
18. The method of claim 15 , wherein at least one stored memory request is a write request, the trigger comprises detecting that a number of write requests stored in the first queue is greater than or equal to a threshold value, and the memory controller is configured to increase a priority of each write request stored in the first queue and the second queue responsive to the trigger.
19. The method of claim 15 , wherein at least one stored memory request is an isochronous memory request, the trigger comprises detecting that at least one isochronous memory request has been pending in the first queue for at least a predetermined time period, and the memory controller is configured to increase a priority of each isochronous memory request stored in the first queue and the second queue responsive to the trigger.
20. The method of claim 15 , wherein at least one stored memory request is a prefetch request, the trigger comprises detecting a demand read request whose address matches an address of a stored prefetch request, and the memory controller is configured to increase a priority of each stored prefetch request in the first queue and the second queue whose address matches the address of the demand read request responsive to the trigger.
21. The memory controller of claim 3 , wherein if a priority of a request in the first queue that corresponds to a request stored in the second queue is changed, a priority of the corresponding request in second queue is also changed.