IP Library › Granted Patent US 7,882,302
Granted Patent B2
US 7,882,302 · App. 11/949,859 · Granted Feb 1, 2011

Method and system for implementing prioritized refresh of DRAM based cache

Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 7,882,302
App. No.
11/949,859
Granted
Feb 1, 2011
Kind
B2
Abstract

A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.

Claims (27)

1. A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache, the method comprising:

identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and

for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set;

wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.

2. The method of claim 1 , wherein a number, k, of sweeps of the cache performed during the current assessment period is configurable.

3. The method of claim 2 , wherein k=1.

4. The method of claim 2 , wherein k is set to equal to the number of ways in each set of the cache.

5. The method of claim 1 , wherein, for any set for which all ways thereof have been accessed by at least one of a read or write operation during the current assessment period, none of the ways thereof are refreshed during the current assessment period.

6. The method of claim 1 , wherein an access conflict of a given way supercedes refreshing thereof.

7. The method of claim 1 , wherein refreshing of a given way supercedes an access conflict thereto.

8. The method of claim 1 , further comprising determining un-accessed ways during the current assessment period though the use of an access bit incorporated into a cache tag array.

9. The method of claim 8 , wherein data in un-accessed ways during the current assessment period is marked as invalid at the end of the current assessment period.

10. The method of claim 1 , further comprising implementing at least two assessment periods within a time corresponding to a retention time of DRAM cells of the cache.

11. A system for implementing prioritized refresh of a multiple way, set associative DRAM based cache, comprising:

a refresh mechanism associated with the cache;

the refresh mechanism configured to identify, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and

the refresh mechanism further configured to, for each set, refresh only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set;

wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.

12. The system of claim 11 , wherein a number, k, of sweeps of the cache performed during the current assessment period is configurable.

13. The system of claim 12 , wherein k=1.

14. The system of claim 12 , wherein k is set to equal to the number of ways in each set of the cache.

15. The system of claim 11 , wherein, for any set for which all ways thereof have been accessed by at least one of a read or write operation during the current assessment period, none of the ways thereof are refreshed during the current assessment period.

16. The system of claim 11 , wherein an access conflict of a given way supercedes refreshing thereof.

17. The system of claim 11 , wherein refreshing of a given way supercedes an access conflict thereto.

18. The system of claim 11 , wherein the refresh mechanism is further configured to determine un-accessed ways during the current assessment period though the use of an access bit incorporated into a cache tag array.

19. The system of claim 18 , wherein data in un-accessed ways during the current assessment period is marked as invalid at the end of the current assessment period.

20. The system of claim 11 , wherein the refresh mechanism is further configured to implement at least two assessment periods within a time corresponding to a retention time of DRAM cells of the cache.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2007
From: FAUCHER, MARC R.; SANDON, PETER A.; TRAN, ARNOLD S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020192/0387 →
Continuity (1)
Related Publication 20090144491A1 · Jun 4, 2009