IP Library › Granted Patent US 7,882,311
Granted Patent B2
US 7,882,311 · App. 12/704,284 · Granted Feb 1, 2011

Non-snoop read/write operations in a system supporting snooping

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,882,311
App. No.
12/704,284
Granted
Feb 1, 2011
Kind
B2
Abstract

Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.

Claims (50)

1. An apparatus comprising:

a plurality of point-to-point interfaces to communicate with remote processing entities;

a plurality of trackers configured to function as a plurality of queues to store non-snoop read and/or non-snoop write operations in order of reception and categorized by associated priority, the trackers to provide data coherency in a multi-node system including the remote processing entities, wherein the trackers are organized as a two-dimensional queue structure to resolve conflicts between conflicting read and write operations, the trackers to be utilized in processing both non-snoop and snoop operations; and

a control circuit coupled with the plurality of trackers to cause the highest priority, non-conflicted non-snoop read/non-conflicted non-snoop write operation to be performed.

2. The apparatus of claim 1 wherein at least one of the remote processing entities comprises a processing core.

3. The apparatus of claim 1 wherein at least one of the remote processing entities comprises a memory controller.

4. The apparatus of claim 1 wherein one or more of the trackers comprise a register.

5. The apparatus of claim 1 wherein the plurality of queues comprise:

a critical first in, first out (FIFO) queue;

a priority FIFO queue;

an ordered FIFO queue; and

an unordered queue.

6. A system comprising:

a dynamic random access memory (DRAM)

a plurality of point-to-point interfaces to communicate with remote processing entities;

a plurality of trackers configured to function as a plurality of queues to store non-snoop read and/or non-snoop write operations in order of reception and categorized by associated priority, the trackers to provide data coherency in a multi-node system including the remote processing entities, wherein the trackers are organized as a two-dimensional queue structure to resolve conflicts between conflicting read and write operations, the trackers to be utilized in processing both non-snoop and snoop operations; and

a control circuit coupled with the plurality of trackers to cause the highest priority, non-conflicted non-snoop read/non-conflicted non-snoop write operation to be performed utilizing the DRAM.

7. The system of claim 6 wherein at least one of the remote processing entities comprises a processing core.

8. The system of claim 6 wherein at least one of the remote processing entities comprises a memory controller.

9. The system of claim 6 wherein one or more of the trackers comprise a register.

10. The system of claim 6 wherein the plurality of queues comprise:

a critical first in, first out (FIFO) queue;

a priority FIFO queue;

an ordered FIFO queue; and

an unordered queue.

11. A method comprising:

maintaining a plurality of tracking structures organized as at least two or more queues to store posted non-snoop memory access operations, the two or more queues having associated priorities, the trackers to provide data coherency in a multi-node system, wherein the trackers are organized as a two-dimensional queue structure to resolve conflicts between conflicting read and write operations, the trackers to be utilized in processing both non-snoop and snoop operations;

receiving a non-snoop memory access operation;

determining whether a posted non-snoop memory access operation conflicts with the received non-snoop memory access operation; and

halting processing of at least one higher priority queue in favor of a lower priority queue to resolve the conflict between the posted non-snoop memory access operation and the received non-snoop memory access operation.

12. The method of claim 11 , wherein the two or more queues comprise:

a critical first in, first out (FIFO) queue;

a priority FIFO queue;

an ordered FIFO queue; and

an unordered queue.

13. The method of claim 11 wherein the two or more queues comprise one or more general-purpose trackers.

14. The method of claim 13 wherein one or more of the trackers comprise a register.

15. The method of claim 13 wherein one or more of the trackers comprise a memory location.

16. An article comprising a computer-readable medium having stored thereon instructions that, when executed, cause one or more processors to:

maintain a plurality of tracking structures organized as at least two or more queues to store posted non-snoop memory access operations, the two or more queues having associated priorities, the trackers to provide data coherency in a multi-node system, wherein the trackers are organized as a two-dimensional queue structure to resolve conflicts between conflicting read and write operations, the trackers to be utilized in processing both non-snoop and snoop operations;

receive a non-snoop memory access operation;

determine whether a posted non-snoop memory access operation conflicts with the received non-snoop memory access operation; and

halt processing of at least one higher priority queue in favor of a lower priority queue to resolve the conflict between the posted non-snoop memory access operation and the received non-snoop memory access operation.

17. The article of claim 16 , wherein the two or more queues comprise:

a critical first in, first out (FIFO) queue;

a priority FIFO queue;

an ordered FIFO queue; and

an unordered queue.

18. The article of claim 17 wherein the two or more queues comprise one or more general-purpose trackers.

19. The article of claim 18 wherein one or more of the trackers comprise a register.

Continuity (2)
Continuation 1185287500 · Sep 10, 2007
Related Publication 20100146200A1 · Jun 10, 2010