Non-volatile memory device and a method of programming the same

1. A method of programming a non-volatile memory device, the method comprising:

performing a program operation;

performing a program verify read operation; and

performing one of a verify recovery operation and a bit line setup operation simultaneously with a pass/fail determine operation, after the performing of the program verify read operation.

2. The method of claim 1 , wherein the verify recovery operation and the pass/fail determine operation are simultaneously performed.

3. The method of claim 2 , wherein a wired-OR scheme is used during the pass/fail determine operation.

4. The method of claim 3 , wherein the pass/fail determine operation is performed after detecting data through a plurality of bit lines during the program verify read operation.

5. The method of claim 4 , wherein, after the detecting of the data, the bit lines are electrically cut off from latches of a page buffer corresponding to the bit lines.

6. The method of claim 2 , wherein a program voltage is provided during the performing of the program operation, the program voltage being incrementally increased according to a program loop.

7. The method of claim 6 , wherein the performing of the program operation comprises:

activating a high voltage generation circuit to generate word line voltages and bit line voltages necessary for programming the non-volatile memory device; and

loading data to be programmed.

8. The method of claim 7 , wherein the performing of the program operation further comprises performing a bit line setup operation to provide a ground voltage as a program voltage to bit lines connected to a memory cell to be programmed and a power supply voltage as a program inhibit voltage to bit lines connected to a memory cell to be program inhibited.

9. The method of claim 8 , wherein the performing of the program operation further comprises providing a program voltage to a selected word line and a pass voltage to non-selected word lines in order to program the loaded data.

10. The method of claim 9 , further comprising performing a core recovery operation to discharge a voltage level of the word lines and the bit lines into a ground voltage after the performing of the program operation.

11. The method of claim 10 , further comprising:

deactivating the high voltage generation circuit; and

completing the program operation if program pass occurs as a result of the pass/fail determine operation.

12. The method of 11 , further comprising:

increasing a program loop counter value if program fail occurs as a result of the pass/fail determine operation; and

repeating the program operation with an increased program voltage.

13. The method of claim 12 , further comprising completing the program operation when the program loop counter value exceeds a reference value.

14. The method of claim 11 , further comprising performing a verify recovery operation after the performing of the program verify read operation.

15. The method of claim 1 , wherein the bit line setup operation and the pass/fail determine operation are simultaneously performed.

16. A non-volatile memory device comprising:

a memory cell array including memory cells arranged on intersection regions of a plurality of word lines and a plurality of bit lines;

a row decoder receiving an address to select one word line from among the plurality of word lines;

a page buffer temporarily storing data bits to be programmed in the memory cell array or temporarily storing data bits detected from the memory cell array through the bit lines;

a pass/fail check circuit determining whether data values latched in the page buffer are identical to pass data or not during a program verify operation; and

a control logic controlling the row decoder, the page buffer, and the pass/fail check circuit to perform one of a verify recovery operation and a bit line setup operation simultaneously with a pass/fail determine operation, after a verify read operation during a program operation.

17. The memory device of claim 16 , wherein the control logic controls the row decoder, the page buffer, and the pass/fail check circuit to simultaneously perform the verify recovery operation and the pass/fail determine operation.

18. The non-volatile memory device of claim 17 , wherein a wired-OR scheme is used during the pass/fail determine operation.

19. The non-volatile memory device of claim 18 , wherein the pass/fail check circuit comprises:

a precharger precharging a check node to a power supply voltage level in response to a precharge enable signal;

a developer developing data into the check node in response to a developer enable signal, the data being latched in the page buffer; and

a latcher latching a voltage level of the check node in response to a latch enable signal,

wherein the precharge enable signal, the developer enable signal, and the latch enable signal are generated from the control logic during the pass/fail determine operation.

20. The memory device of claim 16 , wherein the control logic controls the row decoder, the page buffer, and the pass/fail check circuit to simultaneously perform the bit line setup operation and the pass/fail determine operation.