Power amplifier, method for controlling power amplifier, and wireless communication apparatus
A power amplifier includes: a distortion compensating circuit that causes a bias circuit to have an output impedance so that a subsequent block bipolar transistor for signal amplification-use has a maximized saturated output power; and a distortion compensating circuit that causes a bias circuit to have an output impedance so that a distortion of an output power of the power amplifier 1 with respect to an input power is canceled by a distortion characteristic of an output power with respect to an input power of the subsequent block bipolar transistor for signal amplification-use which has a maximized saturated output power and a distortion characteristic of an output power with respect to an input power of the preceding block bipolar transistor for signal amplification-use. This makes it possible to provide a power amplifier that allows reduction in saturated output power brought by realization of a highly efficient low-distortion power amplifier.
1. A power amplifier comprising:
a plurality of amplifying blocks each of which includes a bipolar transistor,
an output block bias circuit which is connected to a base terminal of an output block bipolar transistor, and which constitutes an output block of the plurality of amplifying blocks,
a preceding block bias circuit which is connected to a base terminal of a preceding block bipolar transistor, and which constitutes an amplifying block followed by the output block,
an output block distortion compensating circuit that causes the output block bias circuit to have a low output impedance so that the output block bipolar transistor has a maximized saturated output power, and
a preceding block distortion compensating circuit that causes the preceding block bias circuit to have an output impedance so that an amplitude distortion of an output power of the power amplifier with respect to an input power is canceled out by (i) a first amplitude distortion characteristic of an output power with respect to an input power of the output block bipolar transistor which has the maximized saturated output power and (ii) a second amplitude distortion characteristic of the preceding block bipolar transistor.
2. The power amplifier as set forth in claim 1 , wherein:
the preceding block bipolar transistor has the first amplitude distortion characteristic in which its gain decreases with an increase in output power; and
the output block bipolar transistor has the second amplitude distortion characteristic in which its gain increases with an increase in output power.
3. The power amplifier as set forth in claim 1 , wherein
the preceding block distortion compensating circuit is a series circuit in which a resistor and a capacitor are connected in series, and causes the preceding block bias circuit to have a target output impedance by changing at least one of a resistance of the resistor and a capacitance of the capacitor.
4. The power amplifier as set forth in claim 1 , wherein
the output block distortion compensating circuit is a series circuit in which a resistor and a capacitor are connected in series, and causes the output block bias circuit to have a target output impedance by changing at least one of a resistance of the resistor and a capacitance of the capacitor.
5. A wireless communication apparatus comprising:
a power amplifier recited in claim 1 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
6. A wireless communication apparatus comprising:
a power amplifier recited in claim 2 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
7. A wireless communication apparatus comprising:
a power amplifier recited in claim 3 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
8. A power amplifier comprising:
a plurality of amplifying blocks each of which includes a bipolar transistor,
an output block bias circuit which is connected to a base terminal of an output block bipolar transistor, and which constitutes an output block of the plurality of amplifying blocks,
a preceding block bias circuit which is connected to a base terminal of a preceding block bipolar transistor, and which constitutes an amplifying block followed by the output block,
an output block distortion compensating circuit that causes the output block bias circuit to have a low output impedance so that the output block bipolar transistor has a maximized saturated output power, and
a preceding block distortion compensating circuit that causes the preceding block bias circuit to have an output impedance so that an amplitude distortion of an putput power of the power amplifier with respect to an input power is canceled out by (i) a first amplitude distortion characteristic of an output power with respect to an input power of the output block bipolar transistor which has the maximized saturated output power and (ii) a second amplitude distortion characteristic of the preceding block bipolar transistor, wherein
the preceding block distortion compensating circuit is a series circuit in which a resistor and a capacitor are connected in series, and causes the preceding block bias circuit to have a target output impedance by changing at least one of a resistance of the resistor and a capacitance of the capacitor, and wherein
the preceding block distortion compensating circuit is connected in parallel with a preceding block base ballast resistor connected to the base terminal of the preceding block bipolar transistor.
9. A wireless communication apparatus comprising:
a power amplifier recited claim 8 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
10. A wireless communication apparatus comprising:
a power amplifier recited in claim 4 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
11. A power amplifier comprising:
a plurality of amplifying blocks each of which includes a bipolar transistor,
an output block bias circuit which is connected to a base terminal of an output block bipolar transistor, and which constitutes an output block of the plurality of amplifying, blocks,
a preceding block bias circuit which is connected to a base terminal of a preceding block bipolar transistor, and which constitutes an amplifying block followed by the output block,
an output block distortion compensating circuit that causes the output block bias circuit to have a low output impedance so that the output block bipolar transistor has a maximized saturated output power, and
a preceding block distortion compensating circuit that causes the preceding block bias circuit to have an output impedance so that an amplitude distortion of an output power of the power amplifier with respect to an input power is canceled out by (i) a first amplitude distortion characteristic of an output power with respect to an input power of the output block bipolar transistor which has the maximized saturated output power and (ii) a second amplitude distortion characteristic of the preceding block bipolar transistor, wherein
the output block distortion compensating circuit is a series circuit in which a resistor and a capacitor are connected in series, and causes the output block bias circuit to have a target output impedance by changing at least one of a resistance of the resistor and a capacitance of the capacitor, and
wherein
the output block distortion compensating circuit is connected in parallel with an output block base ballast resistor connected to the base terminal of the output block bipolar transistor.
12. A wireless communication apparatus comprising:
a power amplifier recited in claim 11 ; and
a transmitting antenna for receiving an output signal from the power amplifier, and for outputting the output signal outside.
13. A method for controlling a power amplifier,
said power amplifier comprising:
a plurality of amplifying blocks each of which includes a bipolar transistor,
an output block bias circuit which is connected to a base terminal of an output block bipolar transistor, and which constitutes an output block of the plurality of amplifying blocks, and
a preceding block bias circuit which is connected to a base terminal of a preceding block bipolar transistor, and which constitutes an amplifying block followed by the output block,
said method comprising the steps of:
causing the output block bias circuit to have a low output impedance so that the output block bipolar transistor has a maximized saturated output power; and
causing the preceding block bias circuit to have an output impedance so that an amplitude distortion of an output power of the power amplifier with respect to an input power is canceled out by (i) a first amplitude distortion characteristic of an output power with respect to an input power of the output block bipolar transistor which has the maximized saturated output power and (ii) a second amplitude distortion characteristic of the preceding block bipolar transistor.
14. The method as set forth in claim 13 , wherein:
the preceding block bipolar transistor carries out Class A operation or Class AB operation, and
the output block bipolar transistor carries out Class B operation or Class AB operation.