Lateral bipolar junction transistor with reduced base resistance
A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
1. A lateral bipolar junction transistor formed in a semiconductor substrate, comprising:
an emitter region;
a base region surrounding the emitter region;
a gate disposed at least over a portion of the base region;
a collector region having at least one open side and being disposed about a periphery of the base region;
a shallow trench isolation (STI) region disposed about a periphery of the collector region;
a base contact region disposed about a periphery of the STI region; and
an extension region merging with the base contact region and laterally extending to the gate on the at least one open side of the collector region.
2. The lateral bipolar junction transistor according to claim 1 wherein the emitter region has a polygonal shape.
3. The lateral bipolar junction transistor according to claim 1 wherein the lateral bipolar junction transistor is a lateral PNP bipolar transistor and wherein the emitter region is a P + doped region formed in an N well.
4. The lateral bipolar junction transistor according to claim 1 further comprises a first lightly doped drain (LDD) region disposed between the gate and the collector region.
5. The lateral bipolar junction transistor according to claim 4 further comprises a first salicide block layer disposed on or over the first LDD region.
6. The lateral bipolar junction transistor according to claim 5 further comprises a first salicide on a portion of the collector region not covered by the first salicide block layer.
7. The lateral bipolar junction transistor according to claim 4 wherein the first LDD region is P type doped.
8. The lateral bipolar junction transistor according to claim 4 wherein no LDD is provided on an inner edge of the gate adjacent to the emitter region.
9. The lateral bipolar junction transistor according to claim 1 further comprises a second LDD region disposed between the gate and the extension region.
10. The lateral bipolar junction transistor according to claim 9 further comprises a second salicide block layer disposed on or over the second LDD region.
11. The lateral bipolar junction transistor according to claim 10 further comprises a second salicide on a portion of the extension region not covered by the second salicide block layer.
12. The lateral bipolar junction transistor according to claim 9 wherein the second LDD region is P type doped.
13. The lateral bipolar junction transistor according to claim 1 wherein the base contact region is an N + doped base contact region.
14. The lateral bipolar junction transistor according to claim 1 wherein a gate dielectric layer is provided between the gate and the base region.
15. The lateral bipolar junction transistor according to claim 14 wherein the gate dielectric layer is formed simultaneously with formation of gate oxide layer in CMOS devices for input/output (I/O) circuits.
16. The lateral bipolar junction transistor according to claim 1 wherein the extension region is an N + extension region.
17. The lateral bipolar junction transistor according to claim 1 wherein the lateral bipolar junction transistor is a lateral NPN bipolar transistor and wherein the emitter region is an N + doped region.