Method for controlling access of a memory
A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.
1. A memory control method, comprising the steps of:
decoding a read-write command to generate a mode register set (MRS) signal;
decoding a bank-select signal so as to generate a register-select signal, when the mode register set signal is enabled;
selecting at least one register from a plurality of registers according to the register-select signal, and writing an address signal to the selected at least one register; and
selectively enabling an error check function according to a value of the at least one selected register.
2. The memory control method according to claim 1 , further comprising:
decoding a signal on an address bus, so as to generate the address signal and the bank-select signal.
3. The memory control method according to claim 1 , further comprising:
decoding a signal on a command bus, so as to generate the read-write command.
4. The memory control method according to claim 2 , further comprising:
decoding a signal on a command bus, so as to generate the read-write command.
5. The memory control method according to claim 3 , wherein the read-write command at least comprises a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal.
6. The memory control method according to claim 4 , wherein the read-write command at least comprises a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal.
7. The memory control method according to claim 5 , wherein when the row address strobe signal, the column address strobe signal, the chip select signal, and the write enable signal are all logic high, the mode register set signal is enabled.
8. The memory control method according to claim 6 , wherein when the row address strobe signal, the column address strobe signal, the chip select signal, and the write enable signal are all logic high, the mode register set signal is enabled.
9. The memory control method according to claim 1 further comprising the steps of:
latching the address signal and the bank-select signal; and
outputting the latched address signal and the latched bank-select signal, when the mode register set signal is enabled.
10. The memory control method according to claim 7 further comprising:
latching the address signal and the bank-select signal; and
outputting the latched address signal and the latched bank-select signal, when the at least one signal is enabled.
11. The memory control method according to claim 8 , further comprising:
latching the address signal and the bank-select signal; and
outputting the latched address signal and the latched bank-select signal, when the mode register set signal is enabled.