Transistors with laterally extended active regions and methods of fabricating same
A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.
1. A transistor disposed on a substrate in relation to an isolation region, the transistor comprising:
a gate electrode and associated source/drain regions,
wherein the isolation region is disposed in the substrate to define an active region, the isolation region including an upper isolation region defining an upper active region and an lower isolation region defining a lower active region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive slope profile, such that a width of an upper mouth portion of the upper isolation region is less than or equal to a width of a lower sidewall portion of the upper isolation region, and the lower isolation region is formed with smoothly curved concaved sidewalls;
the gate electrode extends through the upper active region into the lower active region; and
the source/drain regions are disposed in the active region on respective sides of the gate electrode.
2. The transistor of claim 1 , wherein the upper active region has, at least in part, a concave sidewall.
3. The transistor of claim 1 , wherein the isolation region is filled with an insulating material, wherein the insulating material comprises:
a first insulating material formed on sidewalls of the upper isolation region; and
a second insulating material filling a center portion of the upper isolation region between the first insulating material, and filling the lower isolation region.
4. The transistor of claim 3 , wherein the insulating material includes at least one void formed in is material structure, wherein the at least one void enhances the insulating nature of the insulating material.
5. The transistor of claim 1 , wherein the lower active region has a width greater than the upper active region.
6. The transistor of claim 1 , wherein the width of the lower isolation region is less than a minimal width of the upper isolation region.
7. A semiconductor memory device comprising:
an array of memory cells and at least one peripheral circuit associated with the array, wherein each memory cell in the array comprises at least one lateral extended transistor, the lateral extended transistor comprising a gate electrode and associated source/drain regions,
wherein each memory cell in the array is formed in an active region of a substrate defined by an isolation region, the isolation region including an upper isolation region defining an upper active region and an lower isolation region defining a lower active region, wherein the lower isolation region is formed with smoothly curved concaved sidewalls;
the gate electrode extends through the upper active region into the lower active region; and,
the source/drain regions are disposed in the active region on respective sides of the gate electrode.
8. The semiconductor memory devices of claim 7 , further comprising a decoder circuit receiving an address signal and selecting one or more of the memory cells in the array in response to the address signal.