Method and apparatus for improving noise power estimate in a WCDMA network
View Patent ↗Method and apparatus for improving a noise power estimate in a wideband CDMA (WCDMA) network are disclosed and may include calculating a total noise power estimate for a downlink channel based on a plurality of control channel bits from a plurality of different types of control channels. The plurality of control channel bits may include at least two of: dedicated physical channel (DPCH) transmit power control (TPC) bits, DPCH pilot bits, and common pilot channel (CPICH) bits. A first noise power estimate may be calculated for the downlink channel based on a plurality of the DPCH TPC bits. A value of at least one of the plurality of DPCH TPC bits may not be known when the at least one of the plurality of DPCH TPC bits is received.
1. A method for signal processing:
the method comprising calculating a total noise power estimate for a downlink channel based on a plurality of control channel bits received via a plurality of different types of control channels, wherein said plurality of control channel bits comprises at least two of: dedicated physical channel (DPCH) transmit power control (TPC) bits, DPCH pilot bits, and common pilot channel (CPICH) bits.
2. The method according to claim 1 :
comprising calculating a first noise power estimate for said downlink channel based on a plurality of said DPCH TPC bits, wherein a value of at least one of said plurality of DPCH TPC bits is not known when said at least one of said plurality of DPCH TPC bits is received.
3. The method according to claim 2 , comprising calculating a second noise power estimate for said downlink channel based on a plurality of said DPCH pilot bits.
4. The method according to claim 3 , comprising calculating said total noise power estimate for said downlink channel based on said calculated first noise power estimate and said calculated second noise power estimate.
5. The method according to claim 4 , comprising:
scaling said calculated second noise power estimate utilizing a scaling factor that is a function of a number of TPC bits per slot to yield a scaled second noise power estimate; and
summing said first noise power estimate and said scaled second noise power estimate to yield said total noise power estimate.
6. The method according to claim 3 , comprising calculating a third noise power estimate for said downlink channel based on a plurality of said CPICH bits.
7. The method according to claim 5 , comprising calculating said total noise power estimate for said downlink channel based on said calculated first noise power estimate, said calculated second noise power estimate, and said calculated third noise power estimate.
8. The method according to claim 1 , comprising summing portions of said plurality of DPCH TPC bits that are received via said downlink channel to generate an in-phase (I) component and a quadrature (Q) component.
9. The method according to claim 8 , comprising:
subtracting said generated I component and said generated Q component to determine said first noise power estimate for said downlink channel; and
squaring said subtracted I component and said generated Q component to determine said first noise power estimate for said downlink channel.
10. The method according to claim 9 :
comprising summing said squared I component and said generated Q component over a plurality of TPC symbols to determine said first noise power estimate for said downlink channel, wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
11. The method according to claim 10 , comprising:
calculating a norm of said summed I component and said generated Q component by dividing said sum of said squared I component and said generated Q component by a number of said plurality of DPCH TPC bits per slot of said downlink channel to determine said first noise power estimate for said downlink channel, wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
12. The method according to claim 1 , comprising:
calculating a mean of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean square estimate;
calculating a mean of a power of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean power estimate; and
subtracting said mean square estimate from said mean power estimate to determine said second noise power estimate for said downlink channel.
13. The method according to claim 1 , comprising adjusting transmit power of a transmitter when said transmitter communicates via said downlink channel based on said total noise power estimate.
14. A system for signal processing, the system comprising:
circuitry that enables calculation of a total noise power estimate for a downlink channel based on a plurality of control channel bits received via a plurality of different types of control channels, wherein said plurality of control channel bits comprises at least two of: dedicated physical channel (DPCH) transmit power control (TPC) bits, DPCH pilot bits, and common pilot channel (CPICH) bits.
15. The system according to claim 14 , wherein said circuitry enables calculation of a first noise power estimate for said downlink channel based on a plurality of said DPCH TPC bits, wherein a value of at least one of said plurality of DPCH TPC bits is not known when said at least one of said plurality of DPCH TPC bits is received.
16. The system according to claim 15 , wherein said circuitry enables calculation of a second noise power estimate for said downlink channel based on a plurality of said DPCH pilot bits.
17. The system according to claim 16 , wherein said circuitry enables calculation of said total noise power estimate for said downlink channel based on said calculated first noise power estimate and said calculated second noise power estimate.
18. The system according to claim 17 , wherein:
said circuitry enables scaling of said calculated second noise power estimate utilizing a scaling factor that is a function of a number of TPC bits per slot to yield a scaled second noise power estimate; and
said circuitry enables summing of said first noise power estimate and said scaled second noise power estimate to yield said total noise power estimate.
19. The system according to claim 16 , wherein said circuitry enables calculation of a third noise power estimate for said downlink channel based on a plurality of said CPICH bits.
20. The system according to claim 18 , wherein said circuitry enables calculation of said total noise power estimate for said downlink channel based on said calculated first noise power estimate, said calculated second noise power estimate, and said calculated third noise power estimate.
21. The system according to claim 14 , wherein said circuitry enables summing of portions of said plurality of DPCH TPC bits that are received via said downlink channel to generate an in-phase (I) component and a quadrature (Q) component.
22. The system according to claim 21 , wherein:
said circuitry enables subtraction of said generated I component and said generated Q component to determine said first noise power estimate for said downlink channel; and
said circuitry enables squaring of said subtracted I component and said generated Q component to determine said first noise power estimate for said downlink channel.
23. The system according to claim 22 , wherein said circuitry enables summing of said squared I component and said generated Q component over a plurality of TPC symbols to determine said first noise power estimate for said downlink channel, wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
24. The system according to claim 23 , wherein said circuitry enables calculation of a norm of said summed I component and said generated Q component by dividing said sum of said squared I component and said generated Q component by a number of said plurality of DPCH TPC bits per slot of said downlink channel to determine said first noise power estimate for said downlink channel, wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
25. The system according to claim 14 , wherein:
said circuitry enables calculating of a mean of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean square estimate;
said circuitry enables calculation of a mean of a power of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean power estimate; and
wherein said circuitry enables subtraction of said mean square estimate from said mean power estimate to determine said second noise power estimate for said downlink channel.
26. The system according to claim 14 , wherein said circuitry enables adjusting of transmit power of a transmitter when said transmitter communicates via said downlink channel based on said total noise power estimate.