IP Library Granted Patent US 7,910,288
Granted Patent B2
US 7,910,288 · App. 10/932,993 · Granted Mar 22, 2011

Mask material conversion

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,910,288
App. No.
10/932,993
Granted
Mar 22, 2011
Kind
B2
Abstract

The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

Claims (23)

1. A method for semiconductor processing, comprising:

forming a plurality of spacers on a substrate by pitch multiplication, the spacers formed of a spacer material, wherein forming the plurality of spacers comprises:

providing a plurality of spaced-apart mandrels;

depositing a blanket layer of the spacer material on the mandrels;

anisotropically etching the spacer material to define the spacers; and

preferentially removing the mandrels;

expanding a volume of the spacer material forming the spacers by converting the spacer material to a material occupying a larger volume than the spacer material;

forming a photodefinable layer extending over the spacers; and

patterning the photodefinable layer.

2. The method of claim 1 , wherein expanding a volume of the spacer material forming the spacers comprises expanding the blanket layer of spacer material during forming a plurality of spacers by pitch multiplication.

3. The method of claim 2 , further comprising:

etching horizontal surfaces to form spacers from the blanket layer of spacer material after expanding the spacer material.

4. The method of claim 2 , wherein forming a plurality of spacers comprises:

expanding the spacer material after anisotropically etching horizontal surfaces.

5. The method of claim 1 , wherein converting the spacer material to the second material comprises oxidizing the spacer material forming the spacers.

6. The method of claim 1 , wherein converting the spacer material to the second material comprises nitriding the spacer material forming the spacers.

7. The method of claim 1 , further comprising exposing an underlying layer to reactants through openings between the spacers.

8. The method of claim 7 , wherein the reactants are etchants.

9. The method of claim 8 , wherein exposing an underlying layer comprises etching amorphous carbon.

10. The method of claim 8 , wherein exposing an underlying layer comprises etching a conductive material in the substrate.

11. The method of claim 1 , further comprising trimming the spacers after expanding a volume of material forming the spacers.

12. The method of claim 1 , wherein the spacers comprise polysilicon or amorphous silicon.

13. The method of claim 1 , wherein expanding the volume of the spacer material enlarges the spacers to a width substantially equal to a critical dimension of conductive interconnect lines subsequently patterned in the substrate using the spacers.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2004
From: ABATCHEV, MIRZAFER K.; SANDHU, GURTEJ
To: MICRON TECHNOLOGY, INC.
Reel/Frame 015769/0275 →
Continuity (1)
Related Publication 20060046200A1 · Mar 2, 2006