IP Library › Granted Patent US 7,910,428
Granted Patent B2
US 7,910,428 · App. 12/164,073 · Granted Mar 22, 2011

Capacitor with pillar type storage node and method for fabricating the same including conductive capping layer

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,910,428
App. No.
12/164,073
Granted
Mar 22, 2011
Kind
B2
Abstract

A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Claims (25)

1. A method for fabricating a capacitor in a semiconductor device, the method comprising:

forming a sacrificial layer with an open region over a substrate;

forming a first conductive layer within the open region to form a storage node that includes a cylindrical portion having an interior crevice;

forming a supporter within the interior crevice such that the supporter is disposed entirely within the interior crevice;

forming a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the interior crevice;

removing the sacrificial layer;

forming a dielectric layer over the storage node; and

forming a plate node on the dielectric layer.

2. The method of claim 1 , wherein:

the forming of the supporter includes

forming an insulation layer to fill the interior crevice, and;

removing a portion of the insulation layer so that the remaining portion of the insulation layer at least partially fills the interior crevice, the remaining portion of the insulation layer being used as the supporter; and

the forming of a capping layer includes

forming a second conductive layer to seal tops of the remaining portion of the insulation layer and the storage node, and

removing a portion of the second conductive layer so that the remaining portion of the second conductive layer is disposed within the open region, the remaining portion of the second conductive layer being used as the conductive capping layer.

3. The method of 2 , wherein the conductive capping layer is disposed entirely within the interior crevice.

4. The method of claim 2 , wherein the conductive capping layer contacts a top surface of the storage node and a top surface of the supporter.

5. The method of claim 2 , wherein the first and second conductive layers comprise the same material.

6. The method of claim 2 , wherein the first and second conductive layers each comprises material containing ruthenium (Ru).

7. The method of claim 6 , wherein the first and second conductive layers each comprises ruthenium (Ru) or ruthenium dioxide (RuO 2 ), or both.

8. The method of claim 1 , wherein the supporter comprises an oxide layer or a nitride layer.

9. The method of claim 1 , wherein the supporter is formed of one material selected from the group consisting of silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), and zirconium oxide (ZrO 2 ).

10. The method of claim 1 , wherein the storage node comprises material containing ruthenium (Ru).

11. The method of claim 10 , wherein the material containing ruthenium (Ru) comprises ruthenium (Ru) or ruthenium oxide (RuO 2 ), or both.

12. The method of claim 3 , wherein a top surface of the conductive capping layer is coplanar with a top surface of the storage node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2008
From: LEE, KEE-JEUNG; SONG, HAN-SANG; KIL, DEOK-SIN; KIM, YOUNG-DAE; KIM, JIN-HYOCK; DO, KWAN-WOO; PARK, KYUNG-WOONG
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 021222/0624 →
Priority Claims (1)
KR 10-2007-0066054 · Jul 2, 2007 · national
Continuity (1)
Related Publication 20090008743A1 · Jan 8, 2009