Three-dimensional memory devices and methods of manufacturing and operating the same
A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
1. A method of accessing memory cells, comprising:
sending a first signal to at least one layer select transistor;
activating the at least one select transistor based on the first signal; and
communicating a signal to one memory cell based on the activated at least one select transistor.
2. The method of claim 1 wherein the at least one select transistor is activated on the same layer as the memory cells.
3. The method of claim 1 wherein the at least one select transistor is activated on a different layer as the memory cells.
4. The method of claim 1 further comprising: addressing, decoding, or debugging one or more memory cells based on the at least one activated layer select transistor.
5. A method of accessing memory cells, comprising:
defining a vertical plane by a plane decoder;
selecting the vertical plane via a select transistor; and
decoding the memory cells in the vertical plane.
6. The method of claim 5 , wherein the vertical plane comprises the memory cells located in a plurality of stacked layers of memory arrays respectively.
7. The method of claim 6 , wherein the vertical plane is perpendicular to each of the stacked layers of memory arrays.
8. The method of claim 6 , wherein the memory cells on the vertical plane and at the same stacked layer of memory array are connected to each other in a series connection manner.
9. The method of claim 6 , wherein the memory cells on the vertical plane and at the same stacked layer of memory array are connected to a same bit line.