Method and apparatus for scrubbing memory
Method and apparatus to scrub memory is disclosed. A patrol request, for example a read/write request, may be raised to the memory command scheduler in an out of order memory controller to scrub the memory. The patrol read/write request may be raised as and when patrol interval timer expires. The patrol read/write request may also be raised based on presence of a transaction in-flight to the memory, retry response from the memory command scheduler and correctable or non-correctable error response from the memory command scheduler. An interrupt may be raised to a processor upon completion response from the memory command scheduler.
1. A method to scrub memory comprising
raising a patrol request to a memory command scheduler in an out of order memory controller;
determining presence of a transaction in-flight to the memory;
receiving a patrol request completion response from the memory command scheduler; and
raising an interrupt request to a processor.
2. The method of claim 1 , wherein raising the patrol request comprises raising the patrol request to the memory command scheduler after expiry of patrol interval time.
3. The method of claim 1 , wherein raising the patrol request comprises raising the patrol request to the memory command scheduler based on completion of patrol interval time.
4. The method of claim 1 , wherein raising the patrol request comprises sending the patrol request based upon presence of the transaction in-flight to the memory.
5. The method of claim 1 , further comprising sending the patrol read request based upon retry response from the memory command scheduler.
6. The method of claim 1 , further comprising raising a patrol write request to the memory command scheduler based upon uncorrectable error response in read data.
7. The method of claim 1 , wherein raising the interrupt request to the processor is based upon a write request completion signal from the memory command scheduler.
8. The method of claim 1 , wherein determining presence of the transaction to the memory comprises determining as to whether there is a transaction in-flight to a rank of the memory.
9. A method to scrub memory comprising
receiving, from a patrol scrub logic, a patrol request in an out of order memory controller;
scheduling the patrol request on a memory, wherein scheduling includes sending a retry response to a patrol scrub logic if the patrol request is rejected; and
sending a patrol request completion response to the patrol scrub logic.
10. The method of claim 9 , wherein scheduling the patrol request on the memory comprises accepting the patrol request received from the patrol scrub logic and scheduling the patrol request on the memory.
11. The method of claim 9 , wherein sending the patrol request comprises sending a patrol request non-completion indication to the patrol scrub logic.
12. An apparatus comprising
a patrol scrub logic to raise a patrol request in an out of order memory controller;
a memory command scheduler to schedule the patrol request on a memory; and
a memory controller data path to check errors and generate a response to be sent to the patrol scrub logic; and
a buffer to generate a retry response with respect to the patrol request based on non-acceptance of the patrol request by the memory command scheduler.
13. The apparatus of claim 12 , the memory controller data path to further generate a write request based on an uncorrectable error present in read data.
14. The apparatus of claim 12 , wherein the patrol scrub logic to raise an interrupt to the processor based on non-acceptance of the write request by the memory command scheduler.
15. A system comprising
a memory to store data;
a chipset to facilitate input-output (I/O) signal to be transmitted to a computer system;
an I/O device to provide instructions to a computer system; and
a processor to raise a patrol request in an out of order memory controller to scrub the memory after an expiry of a patrol interval time.
16. The system of claim 15 , wherein the memory controller is included in the processor.
17. The system of claim 15 , wherein the memory controller is included in the chipset.
18. The system of claim 15 , the processor to further raise a patrol read request based upon presence of a transaction in-flight to the memory.
19. The system of claim 18 , further comprising a patrol scrubber to send the patrol read request based upon a retry response from a memory command scheduler.
20. The system of claim 19 , the patrol scrubber to further raise an interrupt request to the processor based on a patrol write request non-completion signal.
21. The system of claim 15 , the processor to further raise a patrol write request upon an uncorrectable error response in read data.