Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates
View Patent ↗A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.
1. A double-gate field effect transistor, comprising:
a strained silicon channel formed adjacent a source and a drain, the strained silicon channel comprising two separated portions, wherein said two separated portions of the strained silicon channel connect the source and the drain;
a first gate formed over a first vertical outer side of said strained silicon channel;
a second gate formed over a second vertical inner side of said strained silicon channel;
a first gate dielectric formed between said first gate and said strained silicon channel; and
a second gate dielectric formed between said second gate and said strained silicon channel,
wherein said strained-silicon channel is non-planar, and
wherein the first gate is electrically separated from the second gate.
2. The double-gate field transistor of claim 1 , wherein said strained silicon channel thickness is substantially uniform.
3. The double-gate field transistor of claim 1 , wherein said strained silicon channel thickness is set by epitaxial growth.
4. The double-gate field transistor of claim 1 , wherein said strained silicon channel is substantially defect-free.
5. The double-gate field transistor of claim 1 , wherein said strained silicon channel includes a distorted lattice cell.
6. The double-gate field transistor for of claim 1 , wherein said first gate and said second gate are independently controllable.
7. The double-gate field transistor of claim 1 , wherein said strained silicon channel comprises a fin.
8. The double-gate field transistor of claim 7 , further comprising a plurality of fins.
9. The double-gate field transistor of claim 1 , wherein said first gate and said second gate are self-aligned.
10. The double-gate field transistor of claim 1 , wherein said first gate and said second gate are defined in a single lithographic step.
11. The double-gate field transistor of claim 1 , wherein said first gate, said second gate, said source and said drain are self-aligned with respect to each other.
12. The double-gate field transistor of claim 1 , wherein said transistor includes a planarized layer over a top surface of the strained silicon channel.
13. The double-gate field transistor of claim 1 , wherein said strained silicon channel is tensely strained.
14. The double-gate field transistor of claim 1 , wherein said strained silicon channel is compressively strained.
15. The double-gate field transistor according to claim 1 , wherein said first gate comprises at least one chemical element not included in said second gate.
16. The double-gate field transistor according to claim 1 , wherein said first gate dielectric is chemically different than said second gate dielectric.
17. A double-gate field effect transistor, comprising:
a strained silicon channel formed adjacent a source and a drain, the strained silicon channel comprising two separated portions, wherein said two separated portions of the strained silicon channel connect the source and the drain;
a first gate formed over a first vertical outer side of said strained silicon channel;
a second gate formed over a second vertical inner side of said strained silicon channel;
a first gate dielectric formed between said first gate and said strained silicon channel; and
a second gate dielectric formed between said second gate and said strained silicon channel,
wherein said strained-silicon channel comprises a fin, and
wherein the first gate is electrically separated from the second gate.
18. A semiconductor device, comprising:
a strained silicon channel formed adjacent a source and a drain, the strained silicon channel comprising two separated portions, wherein said two separated portions of the strained silicon channel connect the source and the drain;
a first gate formed over a first vertical outer side of said strained silicon channel;
a second gate formed over a second vertical inner side of said strained silicon channel;
a first gate dielectric formed between said first gate and said strained silicon channel;
and a second gate dielectric formed between said second gate and said strained silicon channel,
wherein said first gate dielectric is chemically different than said second gate dielectric.