CMOS semiconductor device and method of fabricating the same
Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained.
1. A Complementary Metal-Oxide Semiconductor (CMOS) semiconductor device including nMOS and pMOS areas, comprising:
gates in the nMOS and pMOS areas and including polycrystalline silicon (poly-Si) capping layers and metal nitride layers underneath the poly-Si capping layers; and
a gate insulating layer underneath at least one of the gates,
wherein the metal nitride layers of the nMOS and pMOS areas are of the same type of material,
a thickness of the metal nitride layer of the nMOS area is less than a thickness of the metal nitride layer of the pMOS area, and
a work function of the metal nitride layer of the nMOS area is less than a work function of the metal nitride layer of the pMOS area.
2. The CMOS semiconductor device of claim 1 , wherein the gate insulating layer includes HfO 2 .
3. The CMOS semiconductor device of claim 2 , wherein the metal nitride layers include a dopant including at least one of C, Cl, F, N, and O.
4. The CMOS semiconductor device of claim 1 , wherein the metal nitride layers include a dopant including at least one of C, Cl, F, N, and O.
5. The CMOS semiconductor device of claim 1 , wherein the metal nitride layers include N and at least one of Ti, Ta, W, Mo, Al, Hf, and Zr.
6. The CMOS semiconductor device of claim 5 , wherein the metal nitride layers include TiN.
7. The CMOS semiconductor device of claim 5 , wherein one of the metal nitride layers includes a plurality of unit metal nitride layers.
8. The CMOS semiconductor device of claim 1 , wherein one of the metal nitride layers includes a plurality of unit metal nitride layers.
9. The CMOS semiconductor device of claim 8 , wherein the metal nitride layer of the pMOS area includes the plurality of unit metal nitride layers, and
the plurality of unit metal nitride layers of the metal nitride layer of the pMOS area include dopants of different densities.
10. The CMOS semiconductor device of claim 7 , wherein the metal nitride layer of the pMOS area includes the plurality of unit metal nitride layers, and
the plurality of unit metal nitride layers of the metal nitride layer of the pMOS area include dopants of different densities.
11. A method of fabricating a CMOS semiconductor device, comprising:
forming a gate insulating layer on a silicon substrate including nMOS and pMOS areas; and
forming gates on the gate insulating layer, the gates including metal nitride layers corresponding to the nMOS and pMOS areas and poly-Si capping layers formed on the metal nitride layers,
wherein the metal nitride layers of the nMOS and pMOS areas are formed of the same type of material,
the metal nitride layer of the pMOS area is thicker than the metal nitride layer of the nMOS area, and
a work function of the metal nitride layer of the pMOS area is greater than a work function of the metal nitride layer of the nMOS area.
12. The method of claim 11 , wherein the forming of the gates includes:
forming a first metal nitride layer on the gate insulating layer;
removing a portion corresponding to the nMOS area from the first metal nitride layer;
forming a second metal nitride layer on the first metal nitride layer and the nMOS area;
forming the poly-Si capping layers on the second metal nitride layer; and
patterning layers stacked on the insulating layer to form the gates corresponding to the nMOS and pMOS areas on the substrate.
13. The method of claim 12 , wherein the first and second metal nitride layers are formed at different process temperatures.
14. The method of claim 13 , wherein the process temperature of the first metal nitride layer is about 100° C. or more lower than the process temperature of the second metal nitride layer.
15. The method of claim 14 , wherein the process temperature of the first metal nitride layer is about 450° C. and the process temperature of the second metal nitride layer is about 680° C.
16. The method of claim 11 , wherein the metal nitride layers include N and at least one selected from the group consisting of Ti, W, Ta, Mo, Al, Hf, and Zr.
17. The method of claim 16 , wherein a dopant of at least one of the metal nitride layers includes at least one of C, Cl, F, N, and O.
18. The method of claim 11 , wherein a dopant of at least one of the metal nitride layers includes at least one of C, Cl, F, N, and O.
19. The method of claim 11 , wherein an interfacial layer is formed on the silicon substrate by cleaning the silicon substrate with ozone gas or ozone water.
20. The method of claim 19 , wherein the interfacial layer has a thickness of about 1.5 nm or less.