Method, apparatus and system, providing a one-time programmable memory device
Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory device having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.
1. A method of reading memory cells containing an anti-fuse element, the memory cells being arranged in a cell array, the method comprising:
selecting a row of memory cells for readout;
charging a storage region of all programmed memory cells in the row in accordance with a programmed state of an anti-fuse element within each memory cell by activating a common gate transistor between each anti-fuse element and storage region; and
reading out output signals associated with the level of charge stored in the storage region of all memory cells in the row.
2. The method of claim 1 , wherein the reading out of the output signals comprises, for each cell:
sampling a signal representing a reset value of the storage region;
sampling a signal representing a value of the storage region set by the state of the anti-fuse element; and
outputting an output signal equal to the difference between the sampled signal value signal and the reset value signal.
3. The method of claim 1 , wherein the output signals are digitized by respective comparators.
4. The method of claim 1 , wherein the output signals are read out by respective sense amplifiers.
5. A memory device, comprising:
a plurality of memory cells arranged in an array of rows and columns, at least one of the memory cells comprising:
a one-time programmable anti-fuse element;
a storage region for storing a charge related to the programmed state of the anti-fuse element, and an amplifier transistor having a gate connected to the storage region for amplifying a signal from the storage region and providing the amplified signal as an output signal;
a plurality of pixel cells arranged in an array of rows and column and integrated with the memory cell array; and
a common readout circuit operable to read output signals from the memory cell and pixel cell arrays.
6. The memory device of claim 5 wherein the one-time programmable anti-fuse element comprises a MOSFET transistor.
7. The memory device of claim 5 wherein the anti-fuse element comprises a capacitor.
8. The memory device of claim 5 , wherein the common readout circuit comprises:
circuitry for reading out the at least one memory cell as a reset state of the storage region and as a signal state of the storage region which is determined by the state of the one-time programmable anti-fuse element.
9. The memory device of claim 5 , wherein the readout circuit further comprises sample and hold circuitry for storing a reset state and signal state of a memory cell or pixel cell, and a differential amplifier for subtracting the signals stored in the sample and hold circuitry.
10. The memory device of claim 5 , wherein the readout circuit comprises a sense amplifier.
11. The memory device of claim 5 , wherein the readout circuit comprises a comparator.
12. The memory device of claim 5 , wherein the readout circuit comprises a readout amplifier.
13. The memory device of claim 5 , wherein the memory cell and pixel cell arrays share common row and column lines.