Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
1. A method for operating a memory device, comprising: controlling data transfer through a memory interface in an asynchronous mode by:
writing data to the memory device at least partially in response to a write enable signal on a first interface contact; and
reading data from the memory device at least partially in response to a read enable signal on a second interface contact; and
controlling data transfer in a synchronous mode by:
transferring data at least partially in response to a clock signal on the first interface contact; and
providing a bidirectional data strobe signal on a third interface contact not utilized in the asynchronous mode; and
switching data transfer from the synchronous mode to the asynchronous mode at least partially in response to detecting the clock signal no longer being a periodic signal corresponding to a predetermined clock frequency and existing for a particular number of clock cycles.
2. The method of claim 1 , wherein the data is transferred to the memory device in the synchronous mode at least partially in response to a signal on the third interface contact.
3. The method of claim 1 , including the synchronous mode being selected at least partially in response to a command.
4. The method of claim 3 , wherein the command is a Set Feature command on an I/O bus used for communicating command, address and data information.
5. The method of claim 1 , including the asynchronous mode being selected at least partially in response to a command.
6. The method of claim 5 , wherein the command is a Get Feature command on an I/O bus used for communicating command, address and data information.
7. The method of claim 1 , including:
detecting the clock signal; and
switching data transfer from the asynchronous mode to the synchronous mode at least partially in response to detecting the clock signal.
8. The method of claim 1 , including powering-up the memory device in the synchronous mode.
9. The method of claim 1 , further comprising transferring data during the synchronous mode at least partially in response to a signal complementary to the bidirectional data strobe signal.
10. The method of claim 1 , further comprising transferring data during the synchronous mode at least partially in response to a signal, complementary to the clock signal, on an interface contact not utilized in asynchronous mode.
11. The method of claim 1 , wherein each of the first, second and third interface contacts are pins.
12. The method of claim 1 , wherein each of the first, second and third interface contacts are pads.
13. The method of claim 1 , wherein the bidirectional data strobe signal is provided by the source of the data being transferred in the synchronous mode.
14. The method of claim 1 , wherein the bidirectional data strobe signal is disabled in the asynchronous mode.
15. A memory device, comprising:
an array of memory cells; and
control circuitry configured for:
controlling data transfer through a number of interface contacts in an asynchronous mode by:
writing data to the memory device at least partially in response to a write enable signal on a first interface contact; and
reading data from the memory device at least partially in response to a read enable signal on a second interface contact; and controlling data transfer in a synchronous mode by:
transferring data at least partially in response to a clock signal on the first interface contact; and
clocking data according to a bidirectional data strobe signal driven by a source of the data in the synchronous mode; and
switching data transfer from the synchronous mode to the asynchronous mode at least partially in response to detecting the clock signal no longer being a periodic signal corresponding to a predetermined clock frequency and existing for a particular number of clock cycles.
16. The memory device of claim 15 , wherein the control circuitry is configured to respond to an unasserted state of a read enable signal as a write signal during the synchronous mode.
17. The memory device of claim 15 , wherein the number of interface contacts utilized in the synchronous mode is only one more than the quantity of interface contacts utilized in the asynchronous mode.
18. The method of claim 17 , wherein the one or more contact is configured to receive a bidirectional data strobe signal during the synchronous mode.