Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
View Patent ↗The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
1. A method of manufacturing a semiconductor device, comprising:
forming openings in a first implant mask located over a bipolar region and a first non-bipolar region of a semiconductor substrate to expose a bipolar region portion and the first non-bipolar region;
conducting a first implant through the openings to place a dopant in the semiconductor substrate to form tubs in the bipolar region portion and tubs in the first non-bipolar region;
forming openings in a second implant mask located over the bipolar region portion and a second non-bipolar region to expose the tubs in the bipolar region portion and expose the second non-bipolar region, wherein the tubs of the bipolar region are collector contact tubs for bipolar transistors and the tubs of the first non-bipolar region being protected by the second implant mask; and
conducting a second implant through the openings to place the dopant in the tubs in the bipolar region and form tubs in the second non-bipolar region, such that the dopant concentration in the tubs of the bipolar region is greater than the dopant concentration in the tubs of the second non-bipolar region.
2. The method recited in claim 1 , wherein the bipolar transistors are vertical bipolar transistors and the tubs in the second non-bipolar region are tubs for NMOS non-bipolar transistors and the method further includes forming a collector for each of the vertical bipolar transistors.
3. The method recited in claim 1 , wherein each of the first and second implants includes a series of implants through each of the first and second masks.
4. The method recited in claim 1 , wherein a dopant dosage of the first implant ranges from about 5E12 atoms/cm 2 to about 5E13 atoms/cm 2 .
5. The method recited in claim 4 , wherein an implant energy of the first implant ranges from about 50 keV to about 300 keV.
6. The method recited in claim 1 , wherein a dopant dosage of the second dopant implant ranges from about 5E12 atoms/cm 2 to about 5E13 atoms/cm 2 .
7. The method recited in claim 6 , wherein an implant energy of the second implant ranges from about 50 keV to about 300 keV.
8. A semiconductor device, comprising:
a bipolar transistor region, including collector contact tubs located in a semiconductor substrate, the collector contact tubs each having a dopant concentration ranging from about 1E17 atoms/cm 3 to about 6E18 atoms/cm 3 , and wherein the depth of the dopant concentrations ranges from about 0 nm to about 1000 nm; and
an non-bipolar transistor region, including transistor tubs located in a semiconductor substrate, source/drains located in each of the transistor tubs, and a gate electrode located over each of the transistor tubs, the transistor tubs having a dopant concentration within the depth range that is less than the collector contact tubs, wherein the vertical bipolar transistors are PNP or NPN vertical bipolar transistors and the transistor tubs are NMOS or CMOS transistor tubs, respectively.
9. The device recited in claim 8 , wherein the dopant concentration of the transistor tubs ranges from about 5E16 atoms/cm 3 to about 3E18 atoms/cm 3 .
10. The device recited in claim 8 , wherein the bipolar transistor region includes vertical bipolar transistors.
11. The device recited in claim 8 , wherein the semiconductor device is an integrated circuit and the semiconductor device further includes:
vertical bipolar transistors, wherein each of the vertical bipolar transistors includes one of the collector contact tubs;
non-bipolar transistors, wherein each of the non-bipolar transistors includes one of the transistor tubs;
dielectric layers located over the non-bipolar transistors and vertical bipolar transistors; and
interconnects located in the dielectric layers that electrically connect the non-bipolar and vertical bipolar transistors.
12. A method of manufacturing a semiconductor device, comprising:
forming openings in a first implant mask located over a vertical bipolar transistor region and a first NMOS or CMOS transistor region of a semiconductor substrate to expose a portion of the vertical transistor bipolar region and the first NMOS or CMOS transistor region;
conducting a first implant through the openings to place a dopant in the semiconductor substrate to form tubs in the portion of the vertical bipolar transistor region and the first NMOS or CMOS transistor region;
forming openings in a second implant mask located over the vertical bipolar transistor region and a second NMOS or CMOS transistor region to expose the tubs in the vertical bipolar transistor region and the second NMOS or CMOS transistor region; and
conducting a second implant through the openings to place the dopant in the tubs of the vertical bipolar transistor region and form tubs in the second NMOS or CMOS transistor region, such that the dopant concentration in the tubs of the vertical bipolar transistor region is greater than the dopant concentration in the tubs of the second NMOS or CMOS transistor region.
13. The method recited in claim 12 , wherein the first and second implants include a series of implants through the first and second masks.
14. The method recited in claim 12 , wherein a dopant dosage of the first implant ranges from about 5E12 atoms/cm 2 to about 5E13 atoms/cm 2 .
15. The method recited in claim 14 , wherein an implant energy of the first implant ranges from about 50 keV to about 300 keV.
16. The method recited in claim 12 , wherein a dopant dosage of the second dopant implant ranges from about 5E12 atoms/cm 2 to about 5E13 atoms/cm 2 .
17. The method recited in claim 16 , wherein an implant energy of the second implant ranges from about 50 keV to about 300 keV.
18. The method recited in claim 12 , wherein the semiconductor device is an integrated circuit and the method further includes:
forming vertical bipolar transistors in the vertical bipolar transistor region;
forming a first group of NMOS or CMOS transistors configured to have a first operating voltage and a second group of NMOS or CMOS transistors having a second operating voltage in the first and second NMOS or CMOS transistor regions, respectively;
forming dielectric layers over the NMOS or CMOS transistors and the vertical bipolar transistors; and
forming interconnects over and within the dielectric layers that electrically connect the NMOS or CMOS transistors and the vertical bipolar transistors.