Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding
A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals. The modulated input signal is integrated using an integration capacitor to form an integrated value and the integrated value is compared to a threshold to form the one or more feedback signals. Parasitic capacitance of the one or more switches is initialized to an initial value prior to each intermittent coupling of the reference signal to the input signal using another non-overlapping clock signal.
1. A method of operating a sigma delta modulator, comprising:
modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals;
integrating the modulated input signal using an integration capacitor to form an integrated value;
amplifying the integrated value;
comparing the integrated value to a threshold to form the one or more feedback signals; and
initializing a parasitic capacitance of the one or more switches to an initial value prior to each intermittent coupling of the reference signal to the input signal using a third non-overlapping clock signal.
2. The method of claim 1 , wherein the reference signal is a common mode voltage.
3. The method of claim 1 , wherein the reference signal is an AC connection to ground.
4. The method of claim 3 , wherein the AC connection to ground is via a capacitor having a value greater than approximately 100 times the parasitic capacitance.
5. The method of claim 1 , wherein the one or more non-overlapping clock signals comprise a first clock signal and a non-overlapping second clock signal, each having a first pulse rate, and the third non-overlapping clock signal has a pulse rate equal to twice the first pulse rate.
6. The method of claim 5 , wherein each pulse of the third non-overlapping clock signal is positioned between each pulse of the first clock signal and the second clock signal, such that none of the pulses overlap another pulse.
7. The method of claim 1 , further comprising:
modulating the amplified integrated value by intermittently coupling a reference signal to the amplified integrated value using a second set of one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals; and
initializing a parasitic capacitance of the second set of one or more switches to an initial value prior to each intermittent coupling of the reference signal to the amplified integrated value using another non-overlapping clock signal.
8. A system comprising a sigma delta modulator, the modulator comprising:
feedback circuitry configured to modulate an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals;
filter circuitry configured to integrate the modulated input signal using an integration capacitor to form an integrated value;
quantizer circuitry coupled to the filter configured to compare the integrated value to a threshold to form the one or more feedback signals; and
initialization circuitry coupled to the feedback circuitry configured to initialize a parasitic capacitance of the one or more switches to an initial value prior to each intermittent coupling of the reference signal to the input signal using a third non-overlapping clock signal.
9. The modulator of claim 8 , wherein the reference signal is a common mode voltage.
10. The modulator of claim 8 , wherein the reference signal is an AC connection to ground.
11. The modulator of claim 10 , wherein the AC connection to ground is via a capacitor having a value greater than approximately 100 times the parasitic capacitance.
12. The modulator of claim 8 , further comprising clock generation circuitry configured to generate the one or more non-overlapping clock signals, wherein the one or more non-overlapping clock signals comprise a first clock signal and a non-overlapping second clock signal, each having a first pulse rate, and the third non-overlapping clock signal has a pulse rate equal to twice the first pulse rate.
13. The modulator of claim 12 , wherein the clock generation circuitry is configured to position each pulse of the third non-overlapping clock signal between each pulse of the first clock signal and the second clock signal, such that none of the pulses overlap another pulse.
14. The modulator of claim 8 , further comprising an amplifier coupled to the filter circuitry configured to amplify the integrated value provided to the quantizer circuitry.
15. The modulator of claim 14 , further comprising:
second feedback circuitry coupled to the amplifier configured to modulate the amplified integrated value by intermittently coupling a reference signal to the amplified integrated value using a second set of one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals; and
second initialization circuitry coupled to the second feedback circuitry configured to initialize a parasitic capacitance of the second set of one or more switches to an initial value prior to each intermittent coupling of the reference signal to the amplified integrated value using the third non-overlapping clock signal.
16. The system of claim 8 being a digital radio, wherein the modulator is an analog to digital converter, further comprising an analog front end module coupled to the modulator for providing the input signal.
17. The system of claim 16 being a cellular telephone, further comprising a digital processing system coupled to an output of the analog to digital converter.