Method and apparatus providing shared pixel straight gate architecture

1. A pixel array comprising:

a plurality of pixel blocks organized into rows and columns, each block comprising:

first, single, second, third, and fourth pixels, each pixel having a respective photosensor for generating photocharges;

a common unitary floating diffusion region shared by the photosensors of the first, second, third, and fourth pixels for storing the generated photocharges from each of the photosensors;

a shared readout circuit connected to said common floating diffusion region; and

first, second, third, and fourth rectilinear transfer gates for selectively transferring photocharges from a photosensor of an associated pixel to the first common floating diffusion region;

wherein each of the transfer gates overlaps an edge of the photosensor in its associated pixel and an edge of a photosensor outside the pixel block and transfers photocharge from the photosensor outside the pixel block to a second common floating diffusion; and

wherein said shared readout circuit of a first block is provided between a first pair of photosensors of said first block which are in adjacent pixels rows and a readout circuit of a second block is provided between a second pair of photosensors of said first block which are in adjacent pixel rows.

2. The pixel array of claim 1 , wherein each of the transfer gates is oriented parallel to the edge of a photosensor which it overlaps.

3. The pixel array of claim 1 further comprising a reset transistor for resetting the charges stored at the common unitary floating diffusion region.

4. The pixel array of claim 1 , wherein the shared readout circuit includes a common source follower transistor having a gate connected to said common unitary floating diffusion region and a common row select transistor for gating the output of said source follower transistor.

5. The pixel array of claim 4 , wherein two of the first, second, third and fourth pixels are adjacent pixels in a column of the array.

6. The pixel array of claim 4 , wherein a single electrical contact is provided between said source follower transistor gate and the common unitary floating diffusion region.

7. The pixel array of claim 1 , wherein two of the first, second, third and fourth pixels are two adjacent pixels in a row of the array.

8. The pixel array of claim 1 , wherein the shared readout circuit is located in an active region located between a first and second pair of photosensors.

9. The pixel array of claim 1 , wherein said common unitary floating diffusion region is centrally located with respect to the photosensors of said first, second, third and fourth pixels.

10. The pixel array of claim 1 , wherein said transfer gates extend in the direction of a column of said array such that each transfer gate overlaps an entire edge of the photosensor in its associated pixel block and an entire edge of a photosensor in another pixel block.

11. The pixel array of claim 1 , wherein said first and second pixels are in a first pixel row of said pixel array and said third and fourth pixels are in a second adjacent pixel row of said pixel array and each of said transfer gates extends to overlap photosensors of pixels in a pixel row of said pixel array other than said first and second pixel rows.

12. The pixel array of claim 1 , wherein each of said transfer gates has a rectangular shape.

13. The pixel array of claim 1 , wherein each said transfer gate extends along an entire edge of an associated photosensor of a block.

14. The pixel array of claim 1 , wherein said transfer gates have a rectangular shape and are aligned such that their respective lengths are oriented in the same direction as pixel columns.

15. An imager comprising:

a plurality of pixel blocks organized into rows and columns, each block comprising:

first, second, third, and fourth photosensors for generating photocharges in response to light;

a common unitary floating diffusion region shared by the first, second, third, and fourth photosensors;

first, second, third, and fourth rectangular transfer gates, each having a length and width, for transferring photocharges to the common floating diffusion region from a respective one of the first, second, third, and fourth photosensors;

a common reset transistor for resetting the charge at the common floating diffusion region; and

a readout circuit comprising at least one common transistor for producing at least one signal representing an amount of charge stored at the common storage node, at least a portion of the readout circuit being located in an active region between the first, second, third, and fourth photosensors;

wherein each of the transfer gates overlaps along its length an edge of its first associated photosensor and an edge of a second associated photosensor in an adjacent block; and

wherein said readout circuit of a first block is provided between a first pair of photosensors of said first block which are in adjacent pixels rows and a readout circuit of a second block is provided between a second pair of photosensors of said first block which are in adjacent pixel rows.

16. The imager of claim 15 , wherein the second associated photosensor is in the same column as the first associated photosensor.

17. The imager of claim 15 , wherein the first, second, third or fourth photosensors each comprise a photodiode.

18. An imaging system comprising:

a pixel array comprising:

a plurality of pixel blocks organized into rows and columns, each block comprising:

first, second, third, and fourth pixels, each pixel having a respective photosensor for generating photocharges;

a common unitary floating diffusion region shared by respective photosensors of the first, second, third, and fourth pixels for storing the generated photocharges;

a shared readout circuit connected to said common floating diffusion region; and

first, second, third, and fourth rectilinear transfer gates for transferring photocharges to the common unitary floating diffusion region from a respective one of the first, second, third, and fourth photosensors;

wherein each photosensor is connected to a ground contact;

wherein each of the transfer gates overlaps an entire edge of the photosensor in its associated pixel and the common unitary floating diffusion region;

wherein each of the transfer gates overlaps a photosensor in an adjacent pixel block and a second common floating diffusion region in the adjacent pixel block; and

wherein said shared readout circuit of a first block is provided between a first pair of photosensors of said first block which are in adjacent pixels rows and a readout circuit of a second block is provided between a second pair of photosensors of said first block which are in adjacent pixel rows.

19. The imaging system of claim 18 , wherein each photosensor is a PNP-type photodiode, and the N-region of each photodiode is electrically grounded.

20. The imaging system of claim 18 , wherein the imaging system is part of a digital camera.

21. The imaging system of claim 18 , wherein the imaging system is part of a digital single-lens reflex camera.

22. The imaging system of claim 18 , wherein the imaging system is part of a digital video camera.