Nonvolatile semiconductor memory device
The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
1. A nonvolatile semiconductor memory device comprising:
a plurality of blocks (BLK) arranged in a first direction;
a plurality of master bit lines (MBL 0 , MBL 1 , . . . MBLm) extending in the first direction, the plurality of master bit lines being arranged across the plurality of blocks;
a plurality of column latches (P 1 , P 2 , N 1 , N 2 ) connected to a respective one of the plurality of master bit lines, each of the plurality of column latches storing a readout data, the plurality of column latches being arranged in a second direction perpendicular to the first direction and in a periphery of the plurality of blocks; and
a plurality of source line drivers ( 31 ), arranged in the first direction in a periphery of the plurality of blocks,
wherein each of the plurality of blocks comprises:
a row of a plurality of non-volatile memory cells arranged in the second direction, each of the non-volatile memory cells having a source, a charge trap layer, and a gate with a gate length less than 0.1 μm;
a block source line extending in the second direction, the block source line being connected the source of all of the non-volatile memory cells and being connected to a corresponding one of the plurality of source line drivers ( 31 ); and
a plurality of sub bit line groups, each of the sub lit line groups including a plurality of sub bit lines (SBL 0 , SBL 1 ), the plurality of sub bit lines (SBL 0 , SBL 1 ) being connected to a corresponding one of the non-volatile memory cells, and being selectively connected to a corresponding one of the plurality of master bit lines through selection gate transistors, each of the selection gate transistors being controlled by a selection line (SG 0 , SG 1 ),
wherein during program operation: sources of all of the plurality of non-volatile memory cells in the row are biased to a high voltage by a corresponding one of the source line drivers, and
wherein during program verify operation, the sources of all of the plurality of non-volatile memory cells in the row are biased to a low voltage by the corresponding one of the source line drivers, thereby a program verification is performed to all of the plurality of non-volatile memory cells in the row in parallel.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the plurality of master bit lines is connected to a discharge transistor (N 8 ) to selectively discharge the plurality of master bit lines during the program operation, the discharge transistor being in response to a corresponding one of the column latches.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein the program verify operation is repeatedly performed.
4. The nonvolatile semiconductor memory device according to claim 1 , wherein:
the gate of the each of the non-volatile memory cells in the row is connected to a word line; and
the word line is biased to a pumped voltage during the program operation by a positive charge pump circuit connected thereto.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the non-volatile memory cells is a MONOS memory cell.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the charge trap layer of each of the non-volatile memory cells is a non-conductive nitride film.
7. A nonvolatile semiconductor memory device comprising:
a plurality of blocks (BLK) arranged in a first direction;
a plurality of master bit lines (MBL 0 , MBL 1 , . . . MBLm) extending in the first direction, the plurality of master bit lines being arranged across the plurality of blocks;
a plurality of column latches (P 1 , P 2 , N 1 , N 2 ) connected to a respective one of the plurality of master bit lines, each of the plurality of column latches storing a readout data, the plurality of column latches being arranged in a second direction perpendicular to the first direction and in a periphery of the plurality of blocks; and
a plurality of source line drivers ( 31 ), arranged in the first direction in a periphery of the plurality of blocks,
wherein each of the plurality of blocks comprises:
a row of a plurality of non-volatile memory cells arranged in the second direction, each of the non-volatile memory cells having a source, a charge trap layer, and a gate with a gate length less than 0.1 μm;
a block source line extending in the second direction, the block source line being connected the source of all of the non-volatile memory cells and being connected to a corresponding one of the plurality of source line drivers ( 31 ); and
a plurality of sub bit lines (SBL 0 , SBL 1 ), each of the plurality of sub bit lines being connected to a corresponding one of the non-volatile memory cells, and being selectively connected to a corresponding one of the plurality of master bit lines through a selection gate transistor controlled by a selection line (SG 0 ),
wherein during program operation: sources of all of the plurality of non-volatile memory cells in the row are biased to a high voltage by a corresponding one of the source line drivers, and
wherein during program verify operation, the sources of all of the plurality of non-volatile memory cells in the row are biased to a low voltage by the corresponding one of the source line drivers, thereby a program verification is performed to all of the plurality of non-volatile memory cells in the row in parallel.
8. The nonvolatile semiconductor memory device according to claim 7 , wherein each of the plurality of master bit lines is connected to a discharge transistor (N 8 ) to selectively discharge the plurality of master bit lines during the program operation, the discharge transistor being in response to a corresponding one of the column latches.
9. The nonvolatile semiconductor memory device according to claim 7 , wherein the program verify operation is repeatedly performed.
10. The nonvolatile semiconductor memory device according to claim 7 , wherein:
the gate of the each of the non-volatile memory cells in the row is connected to a word line; and
the word line is biased to a pumped voltage during the program operation by a positive charge pump circuit connected thereto.
11. The nonvolatile semiconductor memory device according to claim 7 , wherein each of the non-volatile memory cells is a MONOS memory cell.
12. The nonvolatile semiconductor memory device according to claim 7 , wherein the charge trap layer of each of the non-volatile memory cells is a non-conductive nitride film.