IP Library Granted Patent US 7,927,953
Granted Patent B2
US 7,927,953 · App. 12/575,906 · Granted Apr 19, 2011

Nonvolatile semiconductor memory device and method for manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,927,953
App. No.
12/575,906
Granted
Apr 19, 2011
Kind
B2
Abstract

On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.

Claims (22)

1. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

forming a charge storage film, a tunnel insulating film, and a channel film made of a silicon crystal in this order on a gate electrode;

forming a silicon oxynitride layer at an interface between the tunnel insulating film and the channel film by performing thermal treatment in a nitrogen monoxide gas atmosphere;

forming a stacked body by alternately stacking a plurality of interlayer insulating films and the gate electrodes on a substrate;

forming a trench in the stacked body,

the charge storage film, the tunnel insulating film, and the channel film being formed on an inner surface of the trench, and

a cavity being formed in the trench when the thermal treatment is performed, the cavity communicating with outside of the trench, and the channel film being exposed to an inner surface of the cavity.

2. The method according to claim 1 , wherein a condition for the thermal treatment is such that a temperature is 700 to 1200° C. and duration is 1 minute to 1 hour.

3. The method according to claim 1 , wherein the forming the channel film includes:

depositing an amorphous silicon film; and

crystallizing the amorphous silicon film.

4. The method according to claim 1 , wherein the trench is shaped like a groove, and the method further comprises:

dividing the channel film along an extending direction of the trench.

5. The method according to claim 1 , wherein the trench is shaped like a cylinder extending in a stacking direction of the stacked body.

6. The method according to claim 5 , further comprising:

after the thermal treatment, exposing the channel film to the inner surface of the cavity; and

burying silicon in the cavity.

7. The method according to claim 1 , further comprising:

burying an insulating film in the cavity.

8. The method according to claim 1 , further comprising:

forming a charge block film on the gate electrode,

the charge storage film being formed on the charge block film.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2009
From: OZAWA, YOSHIO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023347/0463 →
Priority Claims (1)
JP 2008-314187 · Dec 10, 2008 · national
Continuity (1)
Related Publication 20100140684A1 · Jun 10, 2010