Semiconductor storage device and manufacturing method thereof
A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film.
1. A semiconductor storage device comprising: a semiconductor substrate;
an insulating layer provided on the semiconductor substrate and having an opening;
a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening;
a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series;
a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film.
2. The device according to claim 1 , wherein the semiconductor layer is a single-crystal layer.
3. The device according to claim 1 , wherein the memory cell has a tunnel insulating film provided on the semiconductor layer, a charge storage layer provided on the tunnel insulating film, an inter-gate insulating film provided on the charge storage layer, and a control electrode provided on the inter-gate insulating film.
4. The device according to claim 1 , wherein the semiconductor layer is a silicon layer of a first conductivity type, and each memory cell has the silicon layer serving as a channel body and a pair of source/drain and is configured as a transistor of the first conductivity type having a charge storage layer formed on the channel body and a control gate formed on the charge storage layer, and
the selecting transistor has a channel body region formed in a diffusion layer of a second conductivity type and a channel of the first conductivity type is formed on the channel body region.
5. The device according to claim 1 , wherein an upper surface of the gate electrode of the selecting transistor is flat.
6. The device according to claim 1 , wherein a width of the opening is 200 nm or below.
7. The device according to claim 1 , wherein a maximum value of a depth of the recess is 20 nm or below.
8. The device according to claim 1 , wherein a central part of the recess is flat.
9. The device according to claim 1 , wherein the opening of the insulating layer has a tapered portion where a diameter on the semiconductor layer side becomes larger than a diameter on the semiconductor substrate side.
10. The device according to claim 1 , wherein a thickness of the semiconductor layer falls within a range of 20 to 100 nm.