Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
View Patent ↗A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
1. A program product comprising:
a computer readable medium, and
instructions stored on said medium which are effective, when executing on a computer system coupled to layered memory which has a plurality of layers of cache including a level one cache;
to store standard cache lines in the level one cache;
following an initial delay, to selectively store in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines;
to partition an instruction(s) address presented to the level one cache;
to index the instruction(s) address into a tag array of the level one cache;
to compare the instruction(s) address with the tag array a first time to determine whether a match is found;
if a match is found on the first comparison, then
to determine whether the match is a trace line;
if the match is a trace line, to check the trace length parameter, access the required partitions, and forward the instruction(s) for execution by the central processor;
if the match is a conventional cache line, then
to check the target address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) to execution by the central processor, then
to build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line;
if no match is found on the first comparison, then
masking the least significant bits of the instruction(s) address; and
comparing the masked instruction(s) address with the tag array a second time to determine whether a match is found;
if a match is found on the second comparison; then
if the match is trace line, to declare a miss in the level one cache and fetch instruction(s) from a further level cache, forward the instruction(s) for execution by the central processor, build a new trace line, select a cache line to be replaced and replace the selected cache line;
if the match is not a trace line, to check the trace address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) for execution by the central processor; then
to build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line.
2. A computer program product according to claim 1 wherein the initial delay is determined by the accumulation of a count of processor cycles.
3. A computer program product according to claim 1 wherein the initial delay is determined by the accumulation of a count of instruction(s) executed by the processor.
4. A computer program product according to claim 1 wherein the initial delay is determined by the state of a branch history table showing that a threshold of predictability has been attained.
5. A computer program product according to claim 1 wherein the initial delay is determined by recording a cumulative score for the execution of branches, with the score increasing for each correct prediction and decreasing for each incorrect prediction, and identifying when that score reaches a threshold of correct predictions.
6. A computer program product according to claim 1 wherein the initial delay is determined by recording the execution of branches and identifying when a sliding window of such executed branches reaches a threshold of correct predictions.