IP Library › Granted Patent US 7,935,477
Granted Patent B2
US 7,935,477 · App. 11/948,444 · Granted May 3, 2011

Double patterning strategy for contact hole and trench

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 7,935,477
App. No.
11/948,444
Granted
May 3, 2011
Kind
B2
Abstract

A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including at least one opening therein on the substrate; curing the first resist pattern; forming a second resist pattern on the substrate; forming a material layer on the substrate; and removing the first and second resist patterns to expose the substrate.

Claims (45)

1. A method comprising:

providing a substrate;

forming a first material layer on the substrate;

forming a mask layer on the first material layer;

forming an anti-reflective coating layer on the mask layer;

forming a first resist pattern on the anti-reflective coating layer, the first resist pattern including a first opening therein, exposing the anti-reflective coating layer;

curing the first resist pattern using a hardening process;

forming a second resist pattern on the anti-reflective coating layer in the first opening, such that the first resist pattern is not deformed during a lithography process for forming the second resist pattern, the first and second resist patterns forming a second opening therein, exposing the anti-reflective coating layer;

forming a silicon-rich top material layer on the anti-reflective coating layer in the second opening;

removing the first and second resist patterns; and

etching the anti-reflective coating layer and the mask layer.

2. The method of claim 1 , further comprising etching the-anti-reflective coating layer and the mask layer using the top material layer as a mask.

3. The method of claim 1 , wherein the first material layer comprises silicon, poly-silicon, dielectric material, and/or a conductive material.

4. The method of claim 1 , wherein the curing of the first resist pattern comprises applying, to the first resist pattern, a process selected from the group consisting of thermal curing, ultraviolet (UV) curing, e-beam treatment, ion-implant treatment, and combinations thereof.

5. The method of claim 1 , wherein each of the first and second resist patterns comprises a feature having a thickness ranging from about 600 angstrom to about 800 angstrom and a width ranging from about 400 angstrom to about 500 angstrom.

6. The method of claim 1 , wherein the forming of the silicon-rich top material layer comprises forming the silicon-rich top material layer to include greater than approximately 40% silicon by weight.

7. The method of claim 1 , further comprising etching the top material layer to expose the first and second resist patterns before the removing of the first and second resist patterns.

8. The method of claim 7 , wherein the etching of the top material layer comprises implementing an etchant selected from the group consisting of CF 4 , C 3 F 8 , C 4 F 8 , CHF 3 , CH 2 F 2 and combinations thereof.

9. A method of lithography double patterning, comprising:

forming a first material layer on a substrate;

forming a first resist pattern on the first material layer, the first resist pattern including a plurality of openings;

curing the first resist pattern using a thermal method to harden the first resist pattern;

forming a second resist pattern on the first material layer after the curing of the first resist pattern, such that a lithography process for forming the second resist pattern does not deform the first resist pattern;

forming a second material layer on the first material layer;

removing the first and second resist patterns to expose the first material layer uncovered by the second material layer;

etching the first material layer using the second material layer as a mask, thereby forming a contact hole and/or a trench for forming an interconnect; and

forming a bottom anti-reflective coating (BARC) layer on the first material layer before the forming of the first resist pattern.

10. The method of claim 9 , wherein the forming of the first material layer comprises:

forming a dielectric material layer on the substrate; and

forming a carbon-containing material layer by spin-on coating.

11. The method of claim 9 , wherein the forming of the second material layer comprises forming a silicon-rich dielectric material layer by a spin-on coating process.

12. The method of claim 11 , wherein the silicon-rich dielectric layer comprises silicon in a weight percentage more than about 40%.

13. The method of claim 9 , further comprising removing the second material layer after the etching of the first material layer.

14. The method of claim 9 , wherein the forming of the second resist pattern comprises forming the second resist pattern disposed within the plurality of openings.

15. A method of lithography double patterning, comprising:

forming a plurality of spaced first resist features on a substrate by a first lithography process;

curing the plurality of first resist features before forming a plurality of second resist features, wherein the curing of the plurality of the first resist features comprises applying a process selected from the group consisting of thermal curing, ultraviolet (UV) curing, e-beam treatment, ion-implant treatment, and combinations thereof;

forming a plurality of spaced second resist features by a second lithography process, each of the second resist features being located between a respective pair of adjacent said first resist features;

forming a material layer on the substrate;

removing the first and second resist features to expose the substrate uncovered by the material layer;

etching the substrate using the material layer as a mask, thereby forming a contact hole and/or a trench for forming an interconnect; and

implementing an etch-back process to the material layer before the removing of the first and second resist features.

16. The method of claim 15 , wherein a pitch from one of the first resist features to adjacent one of the second resist features is less than about 50 nm.

17. The method of claim 15 , further comprises coating with a polymeric material the plurality of first resist features before the forming of the plurality of second resist features.

18. The method of claim 15 , further comprises coating the plurality of first resist features using a polymeric material before the forming of the plurality of second resist features.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2007
From: HSU, FENG-CHENG; CHEN, CHUN-KUANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 020182/0401 →
Continuity (1)
Related Publication 20090142701A1 · Jun 4, 2009