LDMOS with self aligned vertical LDD backside drain

1. A field effect transistor comprising:

a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate;

well regions of a second conductivity type disposed within the semiconductor region;

source regions of the first conductivity type disposed in the well regions;

a gate electrode extending over each well region and overlapping a corresponding one of the source regions, each gate electrode being insulated from the underlying well region by a gate dielectric;

at least one LDD region of the first conductivity type disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed; and

a sinker region disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region, the sinker region having a higher dopant concentration than the at least one LDD region, wherein a portion of the sinker region extends laterally in the semiconductor region underneath the gate electrode and beyond an edge of the gate electrode.

2. The field effect transistor of claim 1 wherein the at least one LDD region is self-aligned to gate electrodes between which it is disposed.

3. The field effect transistor of claim 1 wherein the sinker region is fully embedded in the semiconductor region so that it does not reach the upper surface of the semiconductor region.

4. The field effect transistor of claim 1 wherein the semiconductor region comprises two or more epitaxial layers.

5. The field effect transistor of claim 4 wherein the semiconductor region comprises an upper epitaxial layer and a lower epitaxial layer having different dopant concentrations.

6. A field effect transistor comprising:

a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate;

well regions of a second conductivity type disposed within the semiconductor region;

source regions of the first conductivity type disposed in the well regions;

a gate electrode extending over each well region and overlapping a corresponding one of the source regions, each gate electrode being insulated from the underlying well region by a gate dielectric;

at least one LDD region of the first conductivity type disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed; and

a sinker region disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region, the sinker region having a higher dopant concentration than the at least one LDD region, wherein a portion of the sinker region extends laterally in the semiconductor region underneath the gate electrode and beyond an edge of the gate electrode;

wherein the at least one LDD region forms an upper LDD region, the field effect transistor further comprising a lower LDD region of the first conductivity type disposed in the semiconductor region directly underneath the upper LDD region and directly above the sinker region.

7. The field effect transistor of claim 6 wherein the lower LDD region has a higher dopant concentration than the upper LDD region, and is self-aligned to gate electrodes between which it is disposed.

8. A field effect transistor comprising:

a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate;

a well region of a second conductivity type disposed within the semiconductor region;

a source region of the first conductivity type disposed in the well region;

a gate electrode extending over the well region and overlapping the source region, the gate electrode being insulated from the well region by a gate dielectric;

an upper LDD region of the first conductivity type disposed in the semiconductor region adjacent to and in contact with the well region, the upper LDD region being self-aligned to the gate electrode;

a lower LDD region of the first conductivity type disposed in the semiconductor region directly underneath but in contact with the upper LDD region, the lower LDD region being self-aligned to the gate electrode; and

a sinker region disposed in the semiconductor region directly underneath but in contact with the lower LDD region such that the upper and lower LDD regions and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region, the sinker region having a higher dopant concentration than the upper and lower LDD regions.

9. The field effect transistor of claim 8 wherein the sinker region is fully embedded in the semiconductor region so that it does not reach the upper surface of the semiconductor region.

10. The field effect transistor of claim 8 wherein the semiconductor region comprises an upper epitaxial layer and a lower epitaxial layer, the upper epitaxial layer having a lower doping concentration than the lower epitaxial layer, and the lower epitaxial layer having a lower doping concentration than the substrate.

11. The field effect transistor of claim 10 wherein the sinker region extends through both the upper and lower epitaxial layers, and both the upper and lower LDD regions extend in the upper epitaxial layer only.

12. The field effect transistor of claim 8 wherein a portion of the sinker region extends laterally in the semiconductor region directly underneath the gate electrode.