Driver circuit and method for reducing electromagnetic interference

1. A driver circuit for switching a load through a power transistor comprising:

a first current generator controlled by a first signal and structured to generate a current to charge a capacitance of a control terminal of said power transistor during power on of said power transistor;

a second current generator controlled by a second signal, said second generator being structured to generate a current to discharge said capacitance of said control terminal of said power transistor during power off of said power transistor;

a control circuit electrically coupled to said second current generator and configured to be coupled to said control terminal of said power transistor, said control circuit comprising:

a storage element structured to store a voltage value, which is representative of a potential difference between said control terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, and

a discharge circuit structured to generate an additional current to discharge said capacitance of said control terminal of said power transistor during said power off process, said additional current being a function of said stored voltage value, wherein said discharge circuit includes:

a third current generator structured to generate the additional current; and

a differential amplifier having a first input configured to receive said voltage value, a second input configured to receive a value representative of a voltage of said control terminal of said power transistor, and an output, the differential amplifier being structured to generate at its output a control signal for actuating the third generator to deliver said additional current as long as said control signal is nonzero.

2. A driver circuit as claimed in claim 1 , wherein said storage element includes a capacitance, the control circuit further comprising:

a voltage differentiator structured to detect said voltage value; and

sampling means for sampling said voltage value into the capacitance.

3. A driver circuit as claimed in claim 2 , wherein said control circuit further comprises:

a third current generator;

a switch coupled to the third current generator; and

a logical control block configured to, in response to detecting that a voltage in said capacitance of said storage element is zero, control said switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor.

4. A driver circuit as claimed in claim 2 , wherein said sampling means include a switch having a control terminal coupled to the voltage differentiator, the switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value.

5. A driver circuit as claimed in claim 1 , wherein said storage element includes a capacitance and the control circuit further includes sampling means for sampling said voltage value into the capacitance and a voltage differentiator structured to detect said voltage value, the driver circuit further comprising:

first and second switches coupled to said first and second current generators, respectively;

a logical control block coupled to said control circuitry and said first and second switches, said logical control block being configured to receive a first enabling signal for enabling said power transistor and a second enabling signal for enabling said logical control block to control operation of said control circuitry, said logical control block being configured to control:

said first and second current generators via first and second control signals controlling the first and second switches respectively,

said differential amplifier by a third control signal, and

said sampling means by a fourth control signal, which in turn depends on a fifth control signal from said voltage differentiator.

6. A driver circuit as claimed in claim 1 , wherein said control circuit comprises an overdrive block configured to receive said voltage value and provide an overdrive voltage to said control terminal of said power transistor.

7. A power circuit for driving a load, comprising:

a power transistor configured to be coupled to the load; and

a drive circuit coupled to the power transistor and configured to drive the power transistor, the drive circuit including:

a first current generator controlled by a first signal and structured to generate a current to charge a capacitance of a control terminal of said power transistor during power on of said power transistor;

a second current generator controlled by a second signal, said second generator being structured to generate a current to discharge said capacitance of said control terminal of said power transistor during power off of said power transistor;

a control circuit electrically coupled to said second current generator and to said control terminal of said power transistor, said control circuit comprising:

a storage element structured to store a voltage value, which is representative of a potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, and

a discharge circuit structured to generate an additional current to discharge said capacitance of said control terminal of said power transistor during said power off process, said additional current being a function of said stored voltage value, wherein said discharge circuit includes:

a third current generator structured to generate the additional current; and

a differential amplifier having a first input configured to receive said voltage value, a second input configured to receive a value representative of a voltage of said control terminal of said power transistor, and an output, the differential amplifier being structured to generate at its output a control signal for actuating the third generator to deliver said additional current as long as said control signal is nonzero.

8. A power circuit as claimed in claim 7 , wherein said storage element includes a capacitance, the control circuit further comprising:

a voltage differentiator structured to detect said voltage value; and

sampling means for sampling said voltage value into the capacitance.

9. A power circuit as claimed in claim 8 , wherein said control circuit further comprises:

a third current generator;

a switch coupled to the third current generator; and

a logical control block configured to, in response to detecting that a voltage in said capacitance is zero, control said switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor.

10. A power circuit as claimed in claim 8 , wherein said sampling means include a switch having a control terminal coupled to the voltage differentiator, the switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value.

11. A power circuit as claimed in claim 7 , wherein said storage element includes a capacitance and the control circuit further includes sampling means for sampling said voltage value into the capacitance and a voltage differentiator structured to detect said voltage value, the driver circuit further comprising:

first and second switches coupled to said first and second current generators, respectively;

a logical control block coupled to said control circuitry and said first and second switches, said logical control block being configured to receive a first enabling signal for enabling said power transistor and a second enabling signal for enabling said logical control block to control operation of said control circuitry, said logical control block being configured to control:

said first and second current generators via first and second control signals controlling the first and second respectively,

said differential amplifier by a third control signal, and

said sampling means by a fourth control signal, which in turn depends on a fifth control signal from said voltage differentiator.

12. A power circuit as claimed in claim 7 , wherein said control circuit comprises an overdrive block configured to receive said voltage value and provide an overdrive voltage to said control terminal of said power transistor.

13. A power circuit as claimed in claim 7 , wherein said control terminal of the transistor is a gate and the conduction terminal is a source.

14. A power circuit as claimed in claim 7 , wherein the storage element is part of a sample and hold circuit configured to sample the potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in the saturation region.

15. A drive circuit as claimed in claim 1 , wherein the storage element is part of a sample and hold circuit configured to sample the potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in the saturation region.