IP Library › Granted Patent US 7,937,615
Granted Patent B2
US 7,937,615 · App. 11/729,948 · Granted May 3, 2011

Method for improving reliability of multi-core processor computer

Assignee: Hitachi, Ltd.
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Quick Facts
Patent No.
US 7,937,615
App. No.
11/729,948
Granted
May 3, 2011
Kind
B2
Abstract

In a system including a plurality of multi-core processors, a table for managing the processors and cores owned by the processors is provided and a single virtual server is formed by using cores owned by different processors when generating the virtual server. According to the number owned by processors, the number of processors is varied. If a fault preecho in a processor is detected, control is exercised so as not to deliver an execution schedule of a virtualization mechanism to the processor in which the fault preecho has been detected. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to processing of a process or thread in an operating system. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to the operating system.

Claims (39)

1. In a virtualization environment in which a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of multi-core processors each having a plurality of arithmetic cores and the virtualization mechanism is managed by a management server, a multi-core processor controlling method, wherein:

the management server includes:

arithmetic core management information which includes correspondence information between a multi-core processor and an arithmetic core, and state information indicating any fault preecho detected in the multi-core processor or the arithmetic core, and

virtualization mechanism management information which indicates correspondence between an arithmetic core which is not assigned to any virtual server and a multi-core processor having the unassigned arithmetic core, and correspondence between an arithmetic core assigned to a virtual server and a multi-core processor having the assigned arithmetic core; and

the virtualization mechanism includes:

a fault preecho detection mechanism for detecting a fault preecho in a multi-core processor, and

a schedule control mechanism for changing a use schedule of a multi-core processor or an arithmetic core to prevent use of the multi-core processor or the arithmetic core,

when the management server generates a new virtual server, the management server performs method steps comprising:

selecting a plurality of different multi-core processors each having an arithmetic core which is not assigned to any virtual server based on the arithmetic core management information and the virtualization mechanism management information; and

issuing a first order to the virtualization mechanism for assigning the unassigned arithmetic cores owned by the selected multi-core processors to the new virtual server, and

when the fault preecho detection mechanism detects a fault preecho in a multi-core processor or an arithmetic core, the management server performs a method step comprising issuing a second order to the schedule control mechanism to change an execution schedule such that no virtual server is executed on the multi-core processor or the arithmetic core in which the fault preecho is detected.

2. The multi-core processor controlling method according to claim 1 , wherein the virtualization mechanism management information interrelates the virtualization mechanism, a virtual server, a multi-core processor assigned to the virtualization mechanism, and an arithmetic core.

3. The multi-core processor controlling method according to claim 1 , wherein the arithmetic core management information interrelates a multi-core processor, an arithmetic core, and status information with respect to the arithmetic core.

4. A system including a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of multi-core processors each having a plurality of arithmetic cores and the virtualization mechanism is managed by a management server, wherein:

the management server includes:

arithmetic core management information which includes correspondence information between a multi-core processor and an arithmetic core, and state information indicating any fault preecho detected in the multi-core processor or the arithmetic core, and

virtualization mechanism management information which indicates correspondence between an arithmetic core which is not assigned to any virtual server and a multi-core processor having the unassigned arithmetic core, and correspondence between an arithmetic core assigned to a virtual server and a multi-core processor having the assigned arithmetic core;

the virtualization mechanism includes:

a fault preecho detection mechanism for detecting a fault preecho in a multi-core processor, and

a schedule control mechanism for changing a use schedule of a multi-core processor or an arithmetic core to prevent use of the multi-core processor or the arithmetic core;

when the management server generates a new virtual server, the management server:

selects a plurality of different multi-core processors each having an arithmetic core which is not assigned to any virtual server based on the arithmetic core management information and the virtualization mechanism management information, and

issues a first order to the virtualization mechanism for assigning the unassigned arithmetic cores owned by the selected multi-core processors to the new virtual server; and

when the fault preecho detection mechanism detects a fault preecho in a multi-core processor or an arithmetic core, the management server issues a second order to the schedule control mechanism to change an execution schedule such that no virtual server is executed on the multi-core processor or the arithmetic core in which the fault preecho is detected.

5. The system according to claim 4 , wherein the virtualization mechanism management information interrelates the virtualization mechanism, a virtual server, a multi-core processor assigned to the virtualization mechanism, and an arithmetic core.

6. The system according to claim 4 , wherein the arithmetic core management information interrelates a multi-core processor, an arithmetic core, and status information with respect to the arithmetic core.

7. In a virtualization environment in which a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of multi-core processors each having a plurality of arithmetic cores and the virtualization mechanism is managed by a management server, a non-transitory computer-readable medium encoded with a program executable by a computer, the program upon execution causing the computer to function as:

the management server including:

arithmetic core management information which includes correspondence information between a multi-core processor and an arithmetic core, and state information indicating any fault preecho detected in the multi-core processor or the arithmetic core, and

virtualization mechanism management information which indicates correspondence between an arithmetic core which is not assigned to any virtual server and a multi-core processor having the unassigned arithmetic core, and correspondence between an arithmetic core assigned to a virtual server and a multi-core processor having the assigned arithmetic core;

the virtualization mechanism including:

a fault preecho detection mechanism for detecting a fault preecho in a multi-core processor, and

a schedule control mechanism for changing a use schedule of a multi-core processor or an arithmetic core to prevent use of the multi-core processor or the arithmetic core;

when the management server generates a new virtual server, the management server:

selects a plurality of different multi-core processors each having an arithmetic core which is not assigned to any virtual server based on the arithmetic core management information and the virtualization mechanism management information, and

issues a first order to the virtualization mechanism for assigning the unassigned arithmetic cores owned by the selected multi-core processors to the new virtual server; and

when the fault preecho detection mechanism detects a fault preecho in a multi-core processor or an arithmetic core, the management server issues a second order to the schedule control mechanism to change an execution schedule such that no virtual server is executed on the multi-core processor or the arithmetic core in which the fault preecho is detected.

8. The non-transitory computer-readable medium according to claim 7 , wherein the virtualization mechanism management information interrelates the virtualization mechanism, a virtual server, a multi-core processor assigned to the virtualization mechanism, and an arithmetic core.

9. The non-transitory computer-readable medium according to claim 7 , wherein the arithmetic core management information interrelates a multi-core processor, an arithmetic core, and status information with respect to the arithmetic core.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2007
From: TAKAMOTO, YOSHIFUMI; HORIE, TORU
To: HITACHI, LTD.
Reel/Frame 019533/0200 →
Priority Claims (1)
JP 2006-340673 · Dec 19, 2006 · national
Continuity (1)
Related Publication 20080148015A1 · Jun 19, 2008