IP Library Granted Patent US 7,944,743
Granted Patent B2
US 7,944,743 · App. 12/537,470 · Granted May 17, 2011

Methods of making a semiconductor memory device

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,944,743
App. No.
12/537,470
Granted
May 17, 2011
Kind
B2
Abstract

One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Claims (26)

1. A method for making a semiconductor memory device, the method comprising:

providing a semiconductor substrate;

forming shallow-trench-isolations in the semiconductor substrate;

forming floating bodies and a base substrate out of the semiconductor substrate by removing portions of the semiconductor substrate and the shallow-trench-isolations, the floating bodies each being a disconnected portion of the semiconductor substrate held separate from the base substrate by portions of the shallow-trench-isolations which were not removed;

forming a conductive layer between the floating bodies and the base substrate; and

forming MOS transistors each including one of the floating bodies,

wherein the floating body of each of the MOS transistors is adapted to store a data bit during operation of the memory device.

2. The method of claim 1 , further comprising forming a nitride cap on a surface of the semiconductor substrate between the shallow-trench-isolations before forming the floating bodies, the nitride cap further holding the floating bodies separate from the base substrate.

3. The method of claim 1 , wherein the semiconductor substrate comprises a single crystalline silicon.

4. The method of claim 3 , wherein the conductive layer is a polysilicon layer.

5. The method of claim 4 , wherein forming the conductive layer comprises depositing polysilicon into gaps formed between the floating bodies such that the conductive layer is self-aligned to the floating bodies.

6. A method for making a semiconductor memory device, the method comprising:

providing a semiconductor substrate;

forming isolation regions in the semiconductor substrate;

forming floating bodies and a base substrate out of the semiconductor substrate by removing portions of the semiconductor substrate and the isolation regions, the floating bodies each being a disconnected portion of the semiconductor substrate held separate from the base substrate by portions of the isolation regions which were not removed;

forming conductive material between the floating bodies and the base substrate; and

forming field effect transistors each including one of the floating bodies.

7. The method of claim 6 wherein forming the conductive material comprises forming voids in the conductive material.

8. The method of claim 7 comprising forming the voids underneath the floating bodies.

9. The method of claim 8 wherein the respective voids are received underneath only a portion of the floating bodies.

10. The method of claim 7 comprising forming the voids to respectively extend from one isolation region to another isolation region.

11. The method of claim 7 comprising forming the voids underneath the floating bodies, and to respectively extend from one isolation region to another isolation region.

12. The method of claim 6 comprising forming gates of the field effect transistors to be recessed in the semiconductor substrate.

13. The method of claim 6 comprising forming a dummy gate over the respective isolation regions.

14. The method of claim 13 comprising forming gates of the field effect transistors to be recessed in the semiconductor substrate.

15. The method of claim 6 wherein forming the conductive layer comprises depositing and subsequently recessing conductive material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 11516814 · Sep 7, 2006
Related Publication 20090311845A1 · Dec 17, 2009