Insulated-gate bipolar transistor (IGBT)

1. A semiconductor device in which a collector electrode is provided such that said collector electrode is in contact with one surface side of a semiconductor substrate,

said semiconductor device, comprising:

a first layer portion in which a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of said second conductivity type having a carrier concentration lower than a carrier concentration of said second semiconductor region are multilayered from said one surface side;

a second layer portion including:

a fourth semiconductor region of said first conductivity type multilayered in a partial region of said third semiconductor region, and having a carrier concentration higher than the carrier concentration of said third semiconductor region,

a fifth semiconductor region of said second conductivity type multilayered on said fourth semiconductor region,

a sixth semiconductor region of said first conductivity type multilayered on said fifth semiconductor region, and

a seventh semiconductor region of said second conductivity type multilayered in a partial region of said sixth semiconductor region, and having a carrier concentration higher than carrier concentration of said sixth semiconductor region;

a gate electrode located along said second layer portion via a gate insulating film, said gate insulating film being provided such that said gate insulating film is in contact with said semiconductor regions included in said second layer portion; and

an emitter electrode which is in low-resistance contact with said seventh semiconductor region of said second layer portion,

wherein said gate insulating film is formed along said respective semiconductor regions included in said second layer portion, and on a side surface of a trench, said trench extending toward said first layer portion and reaching said third semiconductor region; and

where a plane density of carrier concentration on a plane whose distance from a surface on said emitter-electrode side is substantially constant and is substantially equal to or higher than 1×10 12 /cm 2 within said fourth semiconductor region.

2. The semiconductor device according to claim 1 , wherein

said trench, on its one side surface, is in contact with said respective semiconductor regions included in said second layer portion, and an eighth semiconductor region of said first conductivity type is in contact with the other side surface of said trench, said eighth semiconductor region being multilayered on said third semiconductor region such that a partial region of said eighth semiconductor region is in contact with said trench, and having a carrier concentration higher than the carrier concentration of said third semiconductor region.

3. The semiconductor device according to claim 2 , wherein

a plurality of said trenches are provided.

4. The semiconductor device according to claim 3 , wherein

spacing between said trenches which are adjacent to each other via said eighth semiconductor region is wider than spacing between said trenches which are adjacent to each other with said second layer portion sandwiched therebetween.

5. The semiconductor device according to claim 1 , wherein

a density of carrier concentration on a plane whose distance from a surface on said emitter-electrode side is constant is equal to or lower than 1×10 17 /cm 3 within said fifth semiconductor region.

6. The semiconductor device according to claim 2 , wherein

a density of carrier concentration on a plane whose distance from a surface on said emitter-electrode side is constant is equal to or larger than 1×10 12 /cm 2 and a carrier concentration is equal to or lower than 1×10 17 /cm 2 within said fifth semiconductor region.