Dielectric film and layer testing
A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.
1. A semiconductor wafer comprising:
a plurality of die regions arranged in an array;
a plurality of kerf regions disposed between the die regions;
a dielectric layer disposed in one of the kerf regions and in one of the die regions;
a first conductive layer disposed adjacent the dielectric layer, and having a first conductive region disposed in the one of the kerf regions, and having a second conductive region disposed in the one of the die regions;
a second conductive layer separated from the first conductive layer by the dielectric layer, and having a third conductive region disposed in the one of the kerf regions, and having a fourth conductive region disposed in the one of the die regions;
a first test pad disposed in the one of the kerf regions;
a first conducting line disposed in the one of the kerf regions and coupling the first test pad to the first conductive region;
a second test pad disposed in the one of the kerf regions;
a second conducting line disposed in the one of the kerf regions and coupling the second test pad to the first conductive region; and
a third test pad disposed in the one of the kerf regions and coupled to the third conductive region.
2. The semiconductor wafer of claim 1 , wherein the dielectric layer comprises a first gate dielectric of a first transistor in the one of the kerf regions, and comprises a second transistor gate dielectric of a second transistor in the one of the die regions, wherein the first conductive region comprises a first gate of the first transistor in the one of the kerf regions, and wherein the second conductive region comprises a second transistor gate of a second transistor in the one of the die regions.
3. The semiconductor wafer of claim 2 , wherein the dielectric layer comprises a first plurality of transistor gate dielectrics in the one of the kerf regions, and comprises a second plurality of transistor gate dielectrics in the one of the die regions, wherein the first conductive region comprises a first plurality of transistor gates in the one of the kerf regions, and wherein the second conductive region comprises a second plurality of transistor gates in the one of the die regions.
4. The semiconductor wafer of claim 1 , wherein the dielectric layer comprises a first capacitor dielectric of a first capacitor in the one of the kerf regions, and comprises a second capacitor dielectric of a second capacitor in the one of the die regions, wherein the first conductive region comprises a first electrode of the first capacitor in the one of the kerf regions, and wherein the second conductive region comprises a second electrode of the second capacitor in the one of the die regions.
5. The semiconductor wafer of claim 4 , wherein the dielectric layer comprises a first plurality of capacitor dielectrics in the one of the kerf regions, and comprises a second plurality of capacitor dielectrics in the one of the die regions, wherein the first conductive region comprises a first plurality of capacitor electrodes in the one of the kerf regions, and wherein the second conductive region comprises a second plurality capacitor electrodes in the one of the die regions.
6. The semiconductor wafer of claim 1 , further comprising:
a third conducting line disposed in the one of the kerf regions and coupling the third test pad to the third conductive region;
a fourth test pad disposed in the one of the kerf regions and coupled to the third conductive region; and
a fourth conducting line disposed in the one of the kerf regions and coupling the fourth test pad to the third conductive region.
7. The semiconductor wafer of claim 6 , further comprising:
a first via coupling the first and second conducting lines to the first conductive region; and
a second via coupling the third and fourth conducting lines to the third conductive region.
8. The semiconductor wafer of claim 1 , wherein the first conductive line has a first width and the second conductive line has a second width different from the first width.
9. The semiconductor wafer of claim 8 , wherein the second width is between about two and ten times narrower than the first width.