Field-effect transistor
At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply wiring on the element separating area couples gate fingers at the end thereof on the opposite side of the arrangement side of the drain coupling portion. A gate edge coupling portion couples two gate fingers adjacent to each other, sandwiching the source ohmic contact at the end thereof on the arrangement side of the drain coupling portion. The gate edge coupling portion does not intersect with the drain ohmic contact and the drain coupling portion.
1. A field-effect transistor comprising:
a semiconductor substrate having an active area and an element separating area surrounding the active area that are determined on a surface portion of the semiconductor substrate;
a plurality of drain ohmic contacts arranged to intersect with the active area on the semiconductor substrate;
a source ohmic contact arranged to intersect with the active area on the semiconductor substrate between two drain ohmic contacts adjacent thereto;
a drain coupling portion arranged on the element separating area of the semiconductor substrate and couples ends of the drain ohmic contacts on the same side thereof;
a gate having at least two gate fingers arranged to intersect with the active area on the semiconductor substrate of areas between a drain ohmic contact and the source ohmic contact, the two gate fingers sandwiching the source ohmic contact;
a gate power supply line arranged on the element separating area of the semiconductor substrate, couples the two gate fingers at ends thereof opposite to the arrangement side of the drain coupling portion, and supplies a gate voltage to the gate fingers; and
an insulating film being formed over the gate and the semiconductor substrate;
a gate edge coupling portion on the insulating film, the gate edge coupling portion coupling the two gate fingers at an end thereof on the arrangement side of the drain coupling portion by conductive vias in the insulating film, the gate edge coupling portion being arranged so as not to intersect with the drain ohmic contact and the drain coupling portion, wherein the gate edge coupling is supported to be a hollow region.
2. The field-effect transistor according to claim 1 ,
wherein the semiconductor substrate comprises:
a bottom substrate containing SiC,
a channel layer formed over the bottom substrate, and
an electron supply layer formed over the channel layer, the electron supply layer providing an electron to the channel layer,
wherein the drain ohmic contact and the source ohmic contact are ohmically coupled to the channel layer,
wherein the gate controls the potential of the channel layer therebelow.