Variable resistance memory device and system
A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
1. A semiconductor memory device comprising:
a memory cell array including a plurality of variable resistance memory cells divided into a first area and a second area;
an input/output circuit configured to access the memory cell array; and
control logic configured to control the input/output circuit to access the first area or the second area in response to an external command,
wherein the input/output circuit accesses the first area in a memory cell unit, and accesses the second area in a page unit.
2. The semiconductor memory device of claim 1 further comprises:
a memory interface configured to control the control logic in response to external control signals and a select signal, wherein the control signals include a command, an address, and data, and the select signal selects between the first area and the second area.
3. The semiconductor memory device of claim 2 , wherein the memory interface converts the control signals into first area access signals or second area access signals in response to the select signal.
4. The semiconductor memory device of claim 2 , wherein the memory interface controls the control logic so that code data or meta data is stored in the first area.
5. The semiconductor memory device of claim 4 , wherein the first area includes a plurality of banks, and the code data and meta data are stored in separate banks.
6. The semiconductor memory device of claim 5 , wherein the memory interface enables one of the code data and the meta data to be written while the other is being read.
7. The semiconductor memory device of claim 4 , wherein the memory interface controls the control logic such that user data is stored in the second area.
8. The semiconductor memory device of claim 1 , wherein the variable resistance memory cells include a plurality of phase change memory cells.
9. A memory system comprising:
a semiconductor memory device including a variable resistance memory cell array divided into a first area and a second area; and
a memory controller configured to access the first area or the second area in response to an external command,
wherein the semiconductor memory device accesses the first area in a memory cell unit, and accesses the second area in a page unit.
10. The memory system of claim 9 further comprises:
a memory interface configured to access the first area or the second area of the variable resistance memory cell array in response to the control signals and a select signal from the memory controller,
wherein the control signals include a command, an address, and data, and the select signal selects one of the first area and the second area.
11. The memory system of claim 10 , wherein the memory interface converts the control signals into first area access signals or second area access signals in response to the select signal.
12. The memory system of claim 10 , wherein the memory controller controls the memory interface so that code data or meta data is stored in the first area of the semiconductor memory device.
13. The memory system of claim 12 , wherein the first area of the semiconductor memory device includes a plurality of banks, and the code data and meta data are stored in separate banks.
14. The memory system of claim 12 , wherein the memory controller enables execution of a write operation directed to one of the code data and the meta data during execution of a read operation directed to the other.
15. The memory system of claim 10 , wherein the memory controller controls the memory interface such that user data is stored in the second area.
16. The memory system of claim 9 , wherein the variable resistance memory cell array includes a plurality of phase change memory cells.
17. The memory system of claim 9 , wherein the memory controller stores area information of the first area and the second area, and detects a storage location of data with reference to the area information.
18. The memory system of claim 17 , wherein the area information is varied by a mode register setting (MRS) or a fuse setting.
19. The memory system of claim 9 , wherein the semiconductor memory device and the memory controller are realized in a single semiconductor integrated circuit.
20. A memory system comprising:
a semiconductor memory device; and
a memory controller configured to supply control signals and a select signal to the semiconductor memory device in response to an external command,
wherein the semiconductor memory device includes:
a variable resistance memory cell array divided into a first area and a second area;
an input/output circuit configured to access the variable resistance memory cell array;
a memory interface configured to convert the control signals into first area access signals or second area access signals in response to the select signal; and
a control logic for controlling the input/output circuit in response to the first area access signals or the second area access signals.
21. The memory system of claim 20 , wherein the control logic accesses the first area in a memory cell unit and accesses the second area in a page unit.
22. The memory system of claim 20 , wherein the input/output circuit comprises:
a row decoder configured to receive an address from the memory interface, and select a word line corresponding to the address;
a column decoder configured to receive an address form the memory interface, and select a bit line corresponding to the address;
a write driver configured to receive a pulse control signal from the control logic and supply a program current to a data line;
a sense amplifier configured to sense a difference between a voltage of a sense line and a reference voltage and read data stored in the memory cell; and
a data input/output buffer configured to receive data from the memory interface or output data to the memory interface, in response to a data input/output signal from the control logic.
23. The memory system of claim 20 , wherein the memory controller controls the memory interface such that code data or meta data is stored in the first area of the variable resistance memory cell array.
24. The memory system of claim 23 , wherein the first area of the semiconductor memory device includes a plurality of banks, and the code data and meta data are stored in separate banks.