IP Library Granted Patent US 7,955,953
Granted Patent B2
US 7,955,953 · App. 11/957,486 · Granted Jun 7, 2011

Method of forming stacked die package

Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 7,955,953
App. No.
11/957,486
Granted
Jun 7, 2011
Kind
B2
Abstract

A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.

Claims (40)

1. A method of packaging semiconductor integrated circuits, comprising the steps of:

providing a transfer film;

forming a patterned, conductive layer on a surface of the transfer film via a photolithography process;

attaching a first semiconductor integrated circuit (IC) to the transfer film, wherein an active side of the first IC is attached to the transfer film;

attaching a second semiconductor IC to the first IC, wherein a bottom side of the second IC is attached to a bottom side of the first IC;

electrically connecting die pads on an active surface of the second IC to the conductive layer with wires;

providing a resin material on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer;

removing the transfer film, thereby exposing the active side of the first IC and the conductive layer;

forming an electrical distribution layer over the active side of the first IC and the conductive layer; and

attaching conductive balls to the electrical distribution layer, wherein the conductive balls allow electrical interconnection to the first and second integrated circuits.

2. The method of packaging semiconductor integrated circuits of claim 1 , wherein the transfer film comprises a polyimide tape.

3. The method of packaging semiconductor integrated circuits of claim 1 , wherein the conductive layer comprises copper.

4. The method of packaging semiconductor integrated circuits of claim 1 , wherein the transfer film has an adhesive thereon and the first IC is attached to the transfer film with the adhesive.

5. The method of packaging semiconductor integrated circuits of claim 1 , wherein the step of attaching the first IC to the second IC includes attaching with one of an epoxy and an adhesive tape.

6. A method of packaging a semiconductor integrated circuit of claim 1 , wherein the step of forming a patterned, conductive layer on a surface of the transfer film comprises:

forming a dry film layer on a surface of the transfer film; forming a pattern in the dry film layer;

depositing a conductive metal layer in the patterned dry film layer; and

stripping the dry film layer.

7. The method of packaging a semiconductor integrated circuit of claim 1 , wherein the step of forming an electrical distribution layer over the active side of the first IC and the conductive layer includes a photolithography process.

8. The method of packaging a semiconductor integrated circuit of claim 7 , wherein the step of forming an electrical distribution layer over the active side of the first IC and the conductive layer further includes a plating process.

9. A method of packaging semiconductor integrated circuits, comprising the steps of:

providing a transfer film;

forming a dry film layer on a surface of the transfer film;

forming a pattern in the dry film layer;

depositing a conductive metal layer in the patterned dry film layer;

stripping the dry film layer, thereby leaving a patterned conductive layer on a surface of the transfer film

attaching a first semiconductor integrated circuit (IC) to the transfer film, wherein an active side of the first IC is attached to the transfer film;

attaching a second semiconductor IC to the first IC, wherein a bottom side of the second IC is attached to a bottom side of the first IC;

electrically connecting die pads on an active surface of the second IC to the conductive layer with wires;

providing a resin material on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer;

removing the transfer film, thereby exposing the active side of the first IC and the conductive layer;

forming an electrical distribution layer over the active side of the first IC and the conductive layer; and

attaching conductive balls to the electrical distribution layer, wherein the conductive balls allow electrical interconnection to the first and second integrated circuits.

10. The method of packaging semiconductor integrated circuits of claim 9 , wherein the transfer film comprises a polyimide tape.

11. The method of packaging semiconductor integrated circuits of claim 9 , wherein the step of forming a pattern in the dry film layer comprises a photolithography process.

12. The method of packaging semiconductor integrated circuits of claim 9 , wherein the conductive metal comprises copper.

13. The method of packaging semiconductor integrated circuits of claim 9 , wherein the transfer film has an adhesive thereon and the first IC is attached to the transfer film with the adhesive.

14. The method of packaging semiconductor integrated circuits of claim 9 , wherein the step of attaching the first IC to the second IC includes attaching with one of an epoxy and an adhesive tape.

15. The method of packaging a semiconductor integrated circuit of claim 9 , wherein the step of forming an electrical distribution layer over the active side of the first IC and the conductive layer includes a photolithography process and a plating process.

16. A semiconductor device formed according to the method of claim 9 .

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0670 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Jul 11, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021217/0368 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2007
From: LO, WAI YEW; YIP, HENG KEONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 020410/0545 →
Continuity (1)
Related Publication 20090152717A1 · Jun 18, 2009