Computational nodes and computational-node networks that include dynamical-nanodevice connections
View Patent ↗Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.
1. A computational node comprising:
input signal lines connected through memristive, nanowire-junctions to one or more input-providing computational nodes;
an output signal line connected through memristive, nanowire-junctions to one or more output-receiving computational nodes;
a leaky integrator that integrates input signals received through the input signal lines and the output signal line;
a thresholder that compares leaky-integrator output to a threshold value;
a clock input; and
a state machine that, based on received thresholder output and clock input, directs state transitions and that generates computation-node spike signals, wherein spike signals include forward spikes output on the output signal line and backward spikes output on the input signal lines.
2. The computational node of claim 1 wherein the conductance of memristive, nanowire-junctions that connect input signal lines and the output signal line to input-providing and output-receiving nodes, respectively, represent edge weights of a computational-node network that includes the computational node.
3. The computational node of claim 1 wherein forward spikes each comprises approximately-equal-magnitude but opposite-polarity voltage pulses over approximately equal time intervals, one in a first phase, the other in a second phase of a three-phase cycle.
4. The computational node of claim 1 wherein backward spikes each comprises approximately-equal-magnitude but opposite-polarity voltage pulses over non-equal time intervals, one in a second phase, the other in a third phase of a three-phase cycle.
5. The computational node of claim 1 wherein state transitions include transitions between four states comprising:
a quiescent processing mode;
an active processing mode;
a quiescent pre-spiking mode; and
a spiking mode.
6. The computational node of claim 5 wherein the node enters the quiescent-processing-mode state upon power-on, from the active-processing-mode state when thresholder output indicates that integrated input signals are below the threshold value, and from the spiking-mode state following generation of a spike signal.
7. The computational node of claim 6 wherein, in the quiescent-processing-mode state, the computational node integrates received signals from input-providing and output-receiving nodes.
8. The computational node of claim 6 wherein, in the spiking-mode state, the computational node generates a spike signal, sets the leaky-integrator output to the negative of the threshold value, and transitions back to the quiescent-processing-mode state.
9. The computational node of claim 5 wherein the node enters the active-processing-mode state, upon receiving a global-clock tick, from the quiescent-processing-mode state.
10. The computational node of claim 9 wherein, in the active-processing-mode state, the computational node decides, based on output from the thresholder, whether to transition back to the quiescent-processing-mode state, when the thresholder output indicates that integrated input signals are below the threshold value, or to transition to the quiescent-pre-spiking-mode state.
11. The computational node of claim 5 wherein the node enters the quiescent-pre-spiking-mode state from the active-processing-mode state when thresholder output indicates that integrated input signals are greater-than-or-equal-to the threshold value.
12. The computational node of claim 11 wherein, in the quiescent-pre-spiking-mode state, the computational node prepares to generate a spike signal.
13. The computational node of claim 5 wherein the node enters the spiking-mode state from the quiescent-pre-spiking-mode state following reception of a next global-clock signal by the node.
14. A computational-node network implemented from computational nodes of claim 1 , the computational-node network comprising:
input signal lines;
one or more output signal lines; and
one or more computational-node layers, each layer comprising a number of computational nodes.
15. The computational-node network of claim 14 wherein an intermediate-level node is connected to lower-level nodes through memristive nanowire junctions connecting a prior-node-input signal line to lower-level-node output signal lines, the prior-node-input signal line connected to a first via of the intermediate-level node.
16. The computational-node network of claim 14 wherein an intermediate-level node is connected to a same-level node that transmits inhibitory signals through a memristive nanowire junction connecting an inhibitory-input signal line to the same-level-node output signal line, the inhibitory-input signal line connected to a second via of the intermediate-level node.
17. The computational-node network of claim 14 wherein an intermediate-level node is connected to a same-level node that transmits excitatory signals through a memristive nanowire junction connecting an excitatory-input signal line to the same-level-node output signal line, the excitatory-input signal line connected to a third via of the intermediate-level node.
18. The computational-node network of claim 14 wherein an intermediate-level node is connected to a next-level node through a memristive nanowire junction connecting the intermediate-level node's output signal line to a next-level-node's prior-node-input signal line, the output signal line connected to a fourth via of the intermediate-level node.
19. The computational-node network of claim 14 wherein computational nodes are implemented in a single silicon-based layer and hierarchically interconnected by a number of nanowire-connection layers equal to the number of node layers.