Confinement techniques for non-volatile resistive-switching memories
Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.
1. A method, comprising:
forming a first electrode adjacent to an interlayer dielectric;
forming a spacer over at least a portion of the interlayer dielectric and at least a portion of the first electrode, wherein the spacer covers a first interface between the interlayer dielectric and the first electrode; and
depositing a metal oxide layer over the spacer and the first electrode, wherein a second interface between the metal oxide layer and the first electrode is smaller than a top surface of the first electrode.
2. The method of claim 1 , further comprising:
forming a second electrode over the metal oxide layer, wherein the second electrode is a different material than the first electrode.
3. The method of claim 1 , wherein the metal oxide layer comprises a bulk-switching material.
4. The method of claim 3 , wherein the bulk-switching material has a bandgap of at least four eV.
5. The method of claim 1 , wherein:
the metal oxide layer is chosen from the group consisting of: hafnium oxide, tantalum oxide, aluminum oxide, yttrium oxide, and zirconium oxide;
the first electrode is chosen from the group consisting of doped silicon, silicide, and titanium nitride; and
the second electrode is chosen from the group consisting of platinum, titanium nitride, ruthenium, ruthenium oxide, iridium, and iridium oxide.
6. The method of claim 1 , wherein the metal oxide layer is not in contact with the interlayer dielectric.
7. The method of claim 1 , wherein the interlayer dielectric surrounds the first electrode.
8. The method of claim 1 , further comprising planarizing the first metal oxide layer such that a top surface of the first metal oxide layer is substantially planar with a top surface of the spacer.