Granted Patent B2

US 7,960,833 · App. 12/049,533 · Granted Jun 14, 2011

Assignee: Marvell World Trade Ltd.

Abstract

Claims (135)

1. An integrated circuit, comprising:

N plane-like metal layers, where N is an integer greater than one;

a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one, and wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes;

a first source;

a first drain;

a second source, wherein at least two of first source, the first drain and the second source are in communication with at least two of the N plane-like metal layers;

a first gate arranged between the first source and the first drain; and

a second gate arranged between the first drain and the second source,

wherein the first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions, and

wherein at least one of the M contact portions has an elliptical shape.

2. The integrated circuit of claim 1 , further comprising a well substrate contact arranged in the first regions.

3. The integrated circuit of claim 1 , wherein at least two of the N plane-like metal layers are coplanar.

4. The integrated circuit of claim 1 , wherein the N plane-like metal layers are located in separate planes.

5. The integrated circuit of claim 1 , further comprising a plurality of local interconnects in communication with the first and second sources and the first drain.

6. The integrated circuit of claim 1 , wherein the integrated circuit implements a power IC, a first one of the M contact portions supplies a first voltage potential to the power IC, a second one of the M contact portions supplies a second voltage potential to the power IC and a third one of the M contact portions receives an output voltage of the power IC.

7. A system comprising the integrated circuit of claim 1 , and further comprising:

a first transmission line in communication with a first one of the M contact portions;

a second transmission line in communication with a second one of the M contact portions;

a third transmission line in communication with a third one of the M contact portions; and

a capacitance in communication with the second transmission line and the third transmission line, wherein the second transmission line supplies a first voltage potential and the third transmission line supplies a second voltage potential.

8. The integrated circuit of claim 1 , further comprising R well substrate contacts arranged in the first regions, where R is an integer greater than one.

9. The integrated circuit of claim 8 , wherein R is an integer that is greater than three and less than seven.

10. The integrated circuit of claim 8 , wherein the R well substrate contacts are associated with respective ones of R transistors.

11. The integrated circuit of claim 1 , wherein the integrated circuit includes a plurality of transistors.

12. The integrated circuit of claim 11 , wherein the transistors include PMOS transistors.

13. The integrated circuit of claim 1 , further comprising:

a second drain; and

a third gate arranged between the second source and the second drain,

wherein the second and third gates define alternating third and fourth regions, the second and third gates are arranged farther apart in the third regions than in the fourth regions.

14. The integrated circuit of claim 13 , wherein the first regions are arranged adjacent to the fourth regions and the second regions are arranged adjacent to the third regions.

15. The integrated circuit of claim 14 , wherein the first and third regions include R well substrate contacts.

16. A method for providing an integrated circuit, the method comprising:

providing N plane-like metal layers, where N is an integer greater than one;

providing a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one;

arranging the first plane-like metal layer and the N plane-like metal layers in separate planes;

providing a first source, a first drain, and a second source;

arranging at least two of the first source, the first drain and the second source to be in communication with at least two of the N plane-like metal layers;

arranging a first gate between the first source and the first drain;

arranging a second gate between the first drain and the second source;

defining alternating first and second regions in the first drain using the first and second gates; and

arranging the first and second gates farther apart in the first regions than in the second regions,

wherein at least one of the M contact portions has an elliptical shape.

17. The method of claim 16 , further comprising arranging a well substrate contact in the first regions.

18. The method of claim 16 , further comprising arranging at least two of the N plane-like metal layers in the same plane.

19. The method of claim 16 , further comprising arranging the N plane-like metal layers in separate planes.

20. The method of claim 16 , further comprising providing a plurality of local interconnects in communication with the first and second sources and the first drain.

21. The method of claim 16 , further comprising:

implementing a power IC using the integrated circuit;

supplying a first voltage potential to the power IC using a first one of the M contact portions;

supplying a second voltage potential to the power IC using a second one of the M contact portions; and

receiving an output voltage of the power IC at a third one of the M contact portions.

22. The method of claim 16 , further comprising:

providing a first transmission line in communication with a first one of the M contact portions;

providing a second transmission line in communication with a second one of the M contact portions;

providing a third transmission line in communication with a third one of the M contact portions; and

providing a capacitance in communication with the second transmission line and the third transmission line, wherein the second transmission line supplies a first voltage potential and the third transmission line supplies a second voltage potential.

23. The method of claim 16 , further comprising arranging R well substrate contacts in the first regions, where R is an integer greater than one.

24. The method of claim 23 , wherein R is an integer that is greater than three and less than seven.

25. The method of claim 23 , wherein the R well substrate contacts are associated with respective ones of R transistors.

26. The method of claim 16 , wherein the integrated circuit includes a plurality of transistors.

27. The method of claim 26 , wherein the transistors include PMOS transistors.

28. The method of claim 16 , further comprising:

arranging a third gate between the second source and a second drain;

defining alternating third and fourth regions using the second and third gates; and

arranging the second and third gates farther apart in the third regions than in the fourth regions.

29. The method of claim 28 , further comprising arranging the first regions adjacent to the fourth regions and the second regions adjacent to the third regions.

30. The method of claim 29 , wherein the first and third regions include R well substrate contacts.

31. An integrated circuit, comprising:

N plane-like metal layers, where N is an integer greater than one;

a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one, and wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes;

a first source;

a first drain;

a second source, wherein at least two of first source, the first drain and the second source are in communication with at least two of the N plane-like metal layers;

a first gate arranged between the first source and the first drain; and

a second gate arranged between the first drain and the second source,

wherein the first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions, and

wherein first and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions.

32. An integrated circuit, comprising:

N plane-like metal layers, where N is an integer greater than one;

a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one, and wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes;

a first source;

a first drain;

a second source, wherein at least two of first source, the first drain and the second source are in communication with at least two of the N plane-like metal layers;

a first gate arranged between the first source and the first drain; and

a second gate arranged between the first drain and the second source,

wherein the first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions, and

wherein first and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.

33. A system, comprising:

an integrated circuit, comprising:

N plane-like metal layers, where N is an integer greater than one;

a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one, and wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes;

a first source;

a first drain;

a second source, wherein at least two of first source, the first drain and the second source are in communication with at least two of the N plane-like metal layers;

a first gate arranged between the first source and the first drain; and

a second gate arranged between the first drain and the second source,

wherein the first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions; and

a leadframe including transmission lines, the transmission lines in communication with at least two of the M contact portions.

34. The system of claim 33 , wherein the integrated circuit and the transmission lines are encased by a mold compound.

35. The system of claim 34 , wherein the leadframe and the integrated circuit implement a quad flat no-lead (QFN) package.

36. A method for providing an integrated circuit, the method comprising:

providing N plane-like metal layers, where N is an integer greater than one;

providing a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one;

arranging the first plane-like metal layer and the N plane-like metal layers in separate planes;

providing a first source, a first drain, and a second source;

arranging at least two of the first source, the first drain and the second source to be in communication with at least two of the N plane-like metal layers;

arranging a first gate between the first source and the first drain;

arranging a second gate between the first drain and the second source;

defining alternating first and second regions in the first drain using the first and second gates; and

arranging the first and second gates farther apart in the first regions than in the second regions,

wherein first and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions.

37. A method for providing an integrated circuit, the method comprising:

providing N plane-like metal layers, where N is an integer greater than one;

providing a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one;

arranging the first plane-like metal layer and the N plane-like metal layers in separate planes;

providing a first source, a first drain, and a second source;

arranging at least two of the first source, the first drain and the second source to be in communication with at least two of the N plane-like metal layers;

arranging a first gate between the first source and the first drain;

arranging a second gate between the first drain and the second source;

defining alternating first and second regions in the first drain using the first and second gates; and

arranging the first and second gates farther apart in the first regions than in the second regions,

wherein first and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.

38. A method for providing an integrated circuit, the method comprising:

providing N plane-like metal layers, where N is an integer greater than one;

providing a first plane-like metal layer that includes M contact portions in communication with the N plane-like metal layers, respectively, where M is an integer greater than one;

arranging the first plane-like metal layer and the N plane-like metal layers in separate planes;

providing a first source, a first drain, and a second source;

arranging at least two of the first source, the first drain and the second source to be in communication with at least two of the N plane-like metal layers;

arranging a first gate between the first source and the first drain;

arranging a second gate between the first drain and the second source;

defining alternating first and second regions in the first drain using the first and second gates;

arranging the first and second gates farther apart in the first regions than in the second regions; and

providing a leadframe including transmission lines, the transmission lines in communication with at least two of the M contact portions.

39. The method of claim 38 , wherein the integrated circuit and the transmission lines are encased by a mold compound.

40. The method of claim 39 , further comprising implementing a quad flat no-lead (QFN) package using the leadframe and the integrated circuit.

Assignments (5)

Continuity (13)