Memory power management systems and methods
Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
1. A memory power management system comprising:
a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode; and
a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
2. The system of claim 1 , wherein an output of the first LDO and the second LDO are coupled together and the first LDO is enabled and the second LDO disabled in the active mode and the first LDO is disabled and the second LDO is enabled in the standby mode.
3. The system of claim 1 , wherein the first supply voltage is greater than the second supply voltage.
4. The system of claim 3 , wherein the first supply voltage has a voltage of about 1.8 volts and the second supply voltage has a voltage of about 0.7 to about 0.8 volts.
5. The system of claim 4 , wherein the first LDO provides an output voltage of about 1.2 volts in the active mode and the second LDO provides an output voltage of about 0.5 volts to about 0.6 volts in the standby mode.
6. The system of claim 1 , wherein second supply voltage is set to provide a voltage to the at least one peripheral circuit that is at a minimum voltage that the at least one peripheral voltage can operate and the second LDO is set to provide a dropout voltage from the second supply voltage that provides an output voltage that is substantially equal to the minimum memory retention voltage.
7. The system of claim 1 , wherein the second LDO provides an output voltage of about 0.4 volts to about 0.5 volts based on a value stored in the system.
8. The system of claim 1 , wherein the memory array comprises a plurality of memory blocks each being configured to be separately selectable between an active mode and a standby mode.
9. The system of claim 1 , further comprising a selectably coupleable diode disposed between a negative supply terminal of the memory block and a negative supply terminal of the first voltage supply, such that a first memory block can be configured to operate in the active mode, while a second memory block can be configured to operate in the standby mode by selecting a respective diode causing the voltage on the negative supply terminal of the memory block to increase by a diode drop.
10. A mobile communication device comprising the system of claim 1 , and further comprising a controller connected to the power management system and a memory, a transceiver, and an input/output module coupled to the controller.
11. An integrated circuit comprising the system of claim 1 .
12. An integrated circuit (IC) comprising:
a memory system comprising:
a memory array; and
one or more peripheral circuits for reading and/or writing to the memory array; and
a power management system comprising:
a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power the memory array during an active mode; and
a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage is at a minimum peripheral voltage for powering the one or more peripheral circuits for reading and/or writing to the memory array.
13. The IC of claim 12 , wherein an output of the first LDO and the second LDO are coupled together and the first LDO is enabled and the second LDO disabled in the active mode and the first LDO is disabled and the second LDO is enabled in the standby mode.
14. The IC of claim 12 , further comprising a respective selectably coupleable diode disposed between a negative supply terminal of each memory block of the memory array and a negative supply terminal of the first voltage supply, such that a first memory block can be configured to operate in the active mode, while a second memory block can be configured to operate in the standby mode by selecting a respective diode causing the voltage on the negative supply terminal of the respective memory block to increase by a diode drop.
15. A mobile communication device comprising the IC of claim 12 , and further comprising a controller connected to the power management system and the memory and a transceiver, and an input/output module coupled to the controller.