Method for producing Si
View Patent ↗The disclosure relates to a method for producing a microelectronic device including a plurality of Si 1-y Ge y based semi-conducting zones (where 0<y≦1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si 1-y Ge y based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.
1. A method for producing a microelectronic device comprising a plurality of Si 1-y Ge y based semi-conducting zones (where 0<y≦1) with different Germanium contents, comprising:
a) forming at least one oxidation mask comprising a set of oxidation masking blocks on a substrate covered with a plurality of Si 1-x Ge x based semi-conducting zones (where 0<x<1 and x<y) having identical compositions, wherein the oxidation masking blocks respectively cover at least one semi-conducting zone of said plurality of Si 1-x Ge x based semi-conducting zones, wherein a plurality of said oxidation masking blocks have different thicknesses different materials, or a combination thereof; and
b) oxidizing said plurality of Si 1-x Ge x based semi-conducting zones through said oxidation mask, inducing a delay in the oxidation of said plurality of Si 1-x Ge x based semi-conducting zones as a function of the thicknesses and compositions of said oxidation masking blocks, and thereby forming Si 1-x Ge x based semi-conducting zones comprising Si 1-y Ge y (with 0<y<1 wherein y>x) with different Germanium concentrations below said oxidation masking blocks.
2. The method according to claim 1 , wherein the oxidation mask comprises a layer or a stack of layers comprising a set of holes, wherein at least several holes of the set of holes have different depths.
3. The method according to claim 2 , wherein the oxidation mask comprises at least one hole revealing a Si 1-x Ge x based semi-conducting zone.
4. The method according to claim 1 , wherein the oxidation mask comprises at least one masking block comprising a first dielectric material, and at least one second masking block comprising a second dielectric material different from the first dielectric material.
5. The method according to claim 1 , wherein the oxidation mask comprises at least one metallic or semi-conductor material.
6. The method according to claim 1 , comprising, prior to said a) forming at least one mask,
forming a perforated layer on the substrate comprising a plurality of holes, and
forming in the holes of the perforated layer, the Si 1-x Ge x based semi-conducting zones.
7. The method according to claim 1 , wherein a Si 1-x Ge x based semi-conductor layer formed on the substrate comprises a plurality of Si 1-x Ge x based semi-conducting zones.
8. The method according to claim 1 , wherein the oxidation mask comprises at least one layer of variable thickness covering the Si 1-x Ge x based semi-conducting zones.
9. The method according to claim 8 , wherein the upper face of the layer of variable thickness forms an angle that is not nil with the main plane of the substrate.
10. The method according to claim 1 , comprising, after said b) oxidizing said plurality of Si 1-x Ge x based semi-conducting zones,
forming at least one second mask different from the first mask, and
oxidizing said plurality of Si 1-x Ge x based semi-conducting zones through the second mask.
11. The method according to claim 1 , wherein the substrate comprises a Si based layer on which the Si 1-x Ge x based semi-conducting zones rest.
12. The method according to claim 1 , further comprising, after said b) oxidizing said plurality of Si 1-x Ge x based semi-conducting zones, forming a gate on one or more said semi-conducting zones.
13. The method according to claim 1 wherein a thickness of said mask ranges between 20 and 1000 nanometers.
14. The method according to claim 1 wherein a thickness of said mask is 100 nanometers.
15. The method according to claim 4 wherein said dielectric material is Si 3 N 4 .
16. The method according to claim 1 , wherein said substrate is a thin Si layer.
17. The method according to claim 1 , further comprising forming a SiO 2 layer on said plurality of Si 1-y Ge y based semi-conducting zones.
18. The method according to claim 17 , wherein a thickness of said SiO2 layer ranges between 0.3 and 3 nanometers.
19. The method according to claim 1 , comprising, prior to said a) forming at least one mask, forming a thin Si based semi-conductor layer on said plurality of Si 1-y Ge y based semi-conducting zones.
20. The method according to claim 19 , wherein a thickness of the thin Si based semi-conductor layer ranges from 1 to 5 nanometers.