IP Library Granted Patent US 7,973,559
Granted Patent B2
US 7,973,559 · App. 12/435,661 · Granted Jul 5, 2011

Method for fabrication of a semiconductor element and structure thereof

Assignee: William Marsh Rice University
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Quick Facts
Patent No.
US 7,973,559
App. No.
12/435,661
Granted
Jul 5, 2011
Kind
B2
Abstract

Re-programmable antifuses and structures utilizing re-programmable antifuses are presented. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Other embodiments of antifuses include an initializing step prior to programming.

Claims (28)

1. An integrated circuit device comprising a configurable interconnect circuit, wherein said configurable interconnect circuit comprises: a first layer of conductive first strips; an insulation layer; a second layer of conductive second strips, wherein the second strips are arranged in a substantially perpendicular orientation to the first strips; and at least one antifuse; wherein the at least one antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it; wherein the second voltage is higher than the first voltage, wherein the insulation layer includes the at least one re-programmable antifuse; and wherein the at least one antifuse is in a region directly above the first strips and directly below the second strips.

2. The integrated circuit device of claim 1 , wherein the at least one antifuse comprises SiO x , wherein x has a value higher than 1 and less than or equal to 2.

3. The integrated circuit device of claim 1 , wherein the at least one antifuse comprises carbon.

4. The integrated circuit device of claim 3 , wherein the at least one antifuse further comprises a sacrificial layer.

5. The integrated circuit device of claim 1 , wherein the second layer further comprises at least one strip of re-programmable antifuse oriented substantially perpendicularly with respect to the second strips.

6. The integrated circuit device of claim 5 , wherein the at least one strip of re-programmable antifuse comprises SiO x , wherein x has a value higher than 1 and less than or equal to 2.

7. The integrated circuit device of claim 5 , wherein the at least one strip of re-programmable antifuse comprises carbon.

8. The integrated circuit device of claim 7 , wherein the at least one strip of re-programmable antifuse further comprises a sacrificial layer.

9. An integrated circuit device comprising:

a configurable interconnect circuit arranged to be configurable by at least one antifuse;

wherein the at least one antifuse is configured to be activated by applying a first voltage across it and to be programmed to conduct by then applying a second voltage across it;

wherein the at least one antifuse is further configured be re-programmed to be non-conducting by applying a third voltage across it;

wherein the third voltage is higher than the second voltage; and

wherein the first voltage is higher than third voltage: and

wherein the configurable interconnect circuit further comprises;

a first layer of conductive first strips;

an insulation layer; and

a second layer of conductive second strips;

wherein the conductive second strips are oriented substantially perpendicularly with respect to the first strips.

10. The integrated circuit device of claim 9 , wherein the insulation layer includes the at least one antifuse; and

wherein the at least one antifuse is in a region directly above the first strips and directly below the second strips.

11. The integrated circuit device of claim 10 , wherein the at least one antifuse comprises SiO x , wherein x is a value higher than 1 and less than or equal to 2.

12. The integrated circuit device of claim 10 , wherein the at least one antifuse comprises carbon.

13. The integrated circuit device of claim 12 , wherein the at least one antifuse further comprises a sacrificial layer.

14. The integrated circuit device of claim 9 , wherein the second layer further comprises one or more strips of re-programmable antifuse oriented substantially perpendicularly with respect to the second strips.

15. The integrated circuit device of claim 14 , wherein the one or more strips of re-programmable antifuse comprise SiO x , wherein x is a value higher than 1 and less than or equal to 2.

16. The integrated circuit device of claim 14 , wherein the one or more strips of re-programmable antifuse comprise carbon.

17. The integrated circuit device of claim 16 , wherein the one or more strips of re-programmable antifuse further comprise a sacrificial layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME FROM MONOLITHIC 3D TO MONOLITHIC 3D INC. PREVIOUSLY RECORDED ON REEL 027798 FRAME 0290. ASSIGNOR(S) HEREBY CONFIRMS THE ENTIRE ENTRY. Recorded Mar 9, 2012
From: OR-BACH, ZVI
To: MONOLITHIC 3D INC.
Reel/Frame 027839/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2012
From: OR-BACH, ZVI
To: MONOLITHIC 3D
Reel/Frame 027798/0290 →
CONFIRMATORY LICENSE Recorded Aug 15, 2011
From: RICE UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 026751/0233 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2011
From: TOUR, JAMES M.; SINITSKIY, ALEXANDER; YAO, JUN; BEITLER, ELVIRA
To: WILLIAM MARSH RICE UNIVERSITY
Reel/Frame 026337/0552 →
Continuity (1)
Related Publication 20100283504A1 · Nov 11, 2010