Verification circuits and methods for phase change memory array
A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.
1. A verification circuit for a phase change memory array, comprising:
a sensing unit, sensing a first sensing voltage from a first memory cell of the phase change memory array according to an enable signal;
a comparator, generating a comparing signal according to the first sensing voltage and a reference voltage to indicate whether the first memory cell is in a reset state;
a control unit, generating a control signal according to the enable signal; an operating unit, generating a first signal according to the control signal to indicate whether the comparator is active; and
an adjusting unit, providing a writing current to the first memory cell and adjusting the writing current according to the control signal until the comparing signal indicates that the first memory cell is in a reset state.
2. The verification circuit as claimed in claim 1 , wherein the comparing signal indicates that the first memory cell is in a non-reset state when the first sensing voltage is smaller than the reference voltage, and the comparing signal indicates that the first memory cell is in a reset state when the first sensing voltage is larger than or equal to the reference voltage.
3. The verification circuit as claimed in claim 2 , wherein when the comparing signal indicates that the first memory cell is in a non-reset state, the adjusting unit gradually increases the writing current according to the control signal.
4. The verification circuit as claimed in claim 1 , wherein the control signal is a pulse signal, and wherein the sensing unit senses the first sensing voltage from the first memory cell when the control signal is at a first voltage level, and the adjusting unit provides the writing current to the first memory cell when the control signal is at a second voltage level.
5. The verification circuit as claimed in claim 4 , further comprising:
a first switch, having a first terminal coupled to the control unit and a second terminal coupled to the adjusting unit, wherein the first switch is controlled to transmit the control signal of the control unit to the adjusting unit according to the comparing signal; and
a second switch coupled between a specific voltage and the second terminal, having a control terminal for receiving the comparing signal.
6. The verification circuit as claimed in claim 5 , further comprising:
a delay unit, delaying the first signal to generate a second signal;
a flip-flop, having a data input terminal coupled to the second terminal, a clock input terminal for receiving the second signal, and a data output terminal for providing a verification signal; and
a determining unit, providing the enable signal to the control unit.
7. The verification circuit as claimed in claim 6 , wherein the adjusting unit further comprises:
a calculating unit, calculating the pulse number of the control signal to generate an adjusting signal with a plurality of bits; and
a writing current generator, generating the writing current which has a current magnitude corresponding to the adjusting signal, and wherein the current magnitude of the writing current is of reference current magnitude when the comparing signal indicates that the first memory cell is in a reset state.
8. The verification circuit as claimed in claim 7 , wherein the adjusting unit further comprises:
a register, storing the reference current magnitude.
9. The verification circuit as claimed in claim 6 , wherein when the comparing signal indicates that the first memory cell is in a reset state, the determining unit provides the enable signal to the sensing unit according to the verification signal such that the sensing unit senses a second sensing voltage from a second memory cell of the phase change memory array according to the enable signal.
10. The verification circuit as claimed in claim 9 , wherein when the comparing signal indicates that the first memory cell is in a reset state, the determining unit provides the enable signal to the control unit according to the verification signal such that the control unit generates the control signal according to the enable signal.
11. The verification circuit as claimed in claim 10 , wherein the adjusting unit provides the writing current with the reference current magnitude to the second memory cell according to the control signal.
12. The verification circuit as claimed in claim 11 , wherein the comparator generates the comparing signal according to the reference voltage and the second sensing voltage corresponding to the reference current magnitude, so as to indicate whether the second memory cell is in a reset state.
13. The verification circuit as claimed in claim 12 , wherein the comparing signal indicates that the second memory cell is in a reset state when the second sensing voltage is larger than or equal to the reference voltage, and wherein the comparing signal indicates that the second memory cell is in a non-reset state when the second sensing voltage is smaller than the reference voltage.
14. The verification circuit as claimed in claim 13 , wherein when the comparing signal indicates that the second memory cell is in a non-reset state, the adjusting unit gradually increases the writing current provided to the second memory cell according to the control signal such that the current magnitude of the writing current is larger than the reference current magnitude.
15. A verification method for a phase change memory array, comprising:
providing a writing current to a first memory cell of the phase change memory array and gradually increasing the writing current until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage;
recording the current magnitude of the writing current as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage;
reading a second memory cell of the phase change memory array to obtain a second sensing voltage;
determining whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage; and
providing the writing current with the reference current magnitude to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state.
16. The verification method as claimed in claim 15 , further comprising:
when the second sensing voltage corresponding to the reference current magnitude is smaller than the reference voltage, gradually increasing the writing current until the second sensing voltage corresponding to the writing current is larger than or equal to the reference voltage.
17. The verification method as claimed in claim 16 , wherein the second memory cell is in a reset state when the second sensing voltage corresponding to the writing current is larger than or equal to the reference voltage, and wherein the second memory cell is in a non-reset state when the second sensing voltage corresponding to the writing current is smaller than the reference voltage.