Asymmetric source/drain junctions for low power silicon on insulator devices
View Patent ↗A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.
1. A method of forming asymmetric p/n junctions in a field effect transistor (FET) device, comprising:
performing an angled dopant implant for the FET device, the FET device having a buried insulator layer formed on a bulk substrate, a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of the FET device, a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET device, the second type of semiconductor material having a different bandgap than the first type of semiconductor material;
wherein a source side p/n junction of the FET device is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET device is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.
2. The method of forming asymmetric p/n junctions in an FET device according to claim 1 , wherein the first type of semiconductor material has a higher bandgap than the second type of semiconductor material.
3. The method of forming asymmetric p/n junctions in an FET device according to claim 2 , wherein the first type of semiconductor material comprises silicon and the second type of semiconductor material comprises silicon germanium.
4. The method of forming asymmetric p/n junctions in an FET device according to claim 1 , wherein the first type of semiconductor material has a lower bandgap than the second type of semiconductor material.
5. The method of forming asymmetric p/n junctions in an FET device according to claim 1 , wherein the FET device comprises a PFET device.
6. A method of forming a field effect transistor (FET) device, comprising:
forming a buried insulator on a bulk substrate;
forming a first type of semiconductor material on the buried insulator layer;
removing portions of the first type of semiconductor material corresponding to source and drain regions of the FET device, and leaving a portion of the first type of semiconductor material corresponding to a body region of the FET device;
forming a second type of semiconductor material over the buried insulator layer, corresponding to the source and drain regions of the FET device, the second type of semiconductor material having a different bandgap than the first type of semiconductor material; and
performing an angled dopant implant such that a source side p/n junction of the FET device is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.
7. The method of forming an FET device according to claim 6 , wherein the first type of semiconductor material has a higher bandgap than the second type of semiconductor material.
8. The method of forming an FET device according to claim 7 , wherein the first type of semiconductor material comprises silicon and the second type of semiconductor material comprises silicon germanium.
9. The method of forming an FET device according to claim 6 , wherein the first type of semiconductor material has a lower bandgap than the second type of semiconductor material.
10. The method of forming an FET device according to claim 6 , wherein the FET device comprises a PFET device.
11. The method of forming an FET device according to claim 6 , further comprising performing a vertical dopant implant.