Semiconductor device
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
1. A semiconductor device comprising:
a package board;
a first LSI connected to the package board including an external I/O interface for performing communication via the package board;
a second LSI provided above the first LSI including a first memory device having a plurality of first memory cells;
a third LSI provided above the first LSI including a first processing unit for performing operations;
a fourth LSI provided above the second LSI and above the third LSI including a second memory device having a plurality of second memory cells;
a fifth LSI provided above the second LSI and the third LSI including a second processing unit for performing operations;
a first through via provided so as to pass through the first LSI, the second LSI, the third LSI, the fourth LSI, and the fifth LSI, so as to connect to the first processing unit and the second processing unit, and so as not to connect to the first memory device and the second memory device.
2. The semiconductor integrated device according to claim 1 , further comprising:
a second through via provided so as to pass through the first LSI, the second LSI, the third LSI, the fourth LSI, and the fifth LSI, and for providing a power supply to the first LSI, the second LSI, the third LSI, the fourth LSI, and the fifth LSI,
wherein in the second LSI, the first through via is provided more closely to the second through via than the first memory device.
3. The semiconductor integrated device according to claim 2 , wherein in the second LSI, the second through via is provided along an outer periphery of the second LSI.