IP Library Granted Patent US 7,978,104
Granted Patent B2
US 7,978,104 · App. 12/665,466 · Granted Jul 12, 2011

Compensation of mismatch errors in a time-interleaved analog-to-digital converter

Assignee: Signal Processing Devices Sweden AB
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,978,104
App. No.
12/665,466
Granted
Jul 12, 2011
Kind
B2
Abstract

A method for the compensation of frequency-response mismatch errors in M-channel time-interleaved ADCs. The compensation is done utilizing a technique that makes use of a number of fixed filters, that approximate differentiators of different orders, and a few variable multipliers that directly correspond to parameters in polynomial models of the M channel frequency responses. A compensated M-channel time-interleaved ADC is based on and can perform the method.

Claims (31)

1. A method for compensating frequency response mismatch errors in an M-channel interleaved analog-to-digital converter (TI-ADC) comprising M ADCs (1 1 −1 M ) in an array and a filter structure connected to the output of the TI-ADC, the method comprising:

selecting M frequency functions of order P,

determining M (P+1) coefficients ε pr ; p=0,1, . . . , P; r=0,1, . . . M−1 of said frequency functions,

choosing an approximation order K, and

computing a compensated output sequence by applying the TI-ADC output to said filter structure containing multipliers with said coefficients ε pr and M fixed filters G p (z), p=1,2, . . . , M.

2. The method according to claim 1 , further comprising:

denoting the channel responses by Q r (jω),

determining the polynomial models of the frequency functions of the channel responses Q r (jω), r=0,1, . . . , M−1 given as

Q r ( jω )=ε 0r (1+ε 1r ×( jω )+ε 2r ×( jω ) 2 + . . . +ε Pr ×( jω ) P ).

3. The method according to claim 1 , further comprising:

choosing a reference channel r ref ,

denoting the channel responses by Q r (jω),

determining polynomial models of the frequency functions Q r (jω)/Q r ref (jω), r=0,1, . . . , M−1 given as:

Q r ( jω )/Q r ref ( jω )=ε 0r (1+ε 1r ×( jω )+ε 2r ×( jω ) 2 + . . . +ε Pr ×( jω ) P ),

wherein p=0,1, . . . , P; r=0,1, . . . , M−1; r≠r ref and ε pr ref is set to ε 0r ref =1 and further ε pr ref =0 for p=1,2, . . . , P.

4. The method according to claim 1 , further comprising:

approximating pth order differentiators G p (z).

5. The method according to claim 1 , further comprising:

optimizing G p (z) simultaneously.

6. A compensated analog-to-digital time-interleaved converter, comprising:

a number of M channels,

each channel including an ADC (1 1 −1 M ), and

a filter structure (2) connected to the output of the M channel TI-ADC,

wherein the converter is configured to carry out a method for compensating frequency response mismatch errors in the converter, the method comprising

selecting M frequency functions of order P,

determining M (P+1) coefficients ε pr ; p=0,1, . . . , P; r=0,1, . . . M−1 of said frequency functions,

choosing an approximation order K, and

computing a compensated output sequence by applying the TI-ADC output to said filter structure containing multipliers with said coefficients ε pr and M fixed filters G p (z), p=1,2, . . . , M.

7. The compensated analog-to-digital converter according to claim 6 , wherein said filter structure comprises a number of fixed filters G p (z) and variable multipliers.

8. The compensated analog-to-digital converter according to claim 6 , wherein the filter structure has G p (z) filters corresponding to pth order differentiators.

9. The compensated analog-to-digital converter according to claim 6 , wherein said filter structure has variable multipliers corresponding to the coefficients ε pr .

Assignments (2)
CHANGE OF NAME Recorded Jul 21, 2017
From: SIGNAL PROCESSING DEVICES SWEDEN AB
To: TELEDYNE SIGNAL PROCESSING DEVICES SWEDEN AB
Reel/Frame 043306/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2010
From: JOHNASSON, HAKAN
To: SIGNAL PROCESSING DEVICES SWEDEN AB
Reel/Frame 023799/0089 →
Continuity (1)
Related Publication 20100192027A1 · Jul 29, 2010