Asynchronous circuit representation of synchronous circuit with asynchronous inputs

1. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input; and

converting an asynchronous output to an asynchronous output operable to update the asynchronous output state upon receipt of a valid data token.

2. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input; and

The method of converting a synchronous circuit to an asynchronous circuit of claim 1 , further comprising converting one or more synchronous clocked inputs or outputs at circuit boundaries to converted synchronous inputs or outputs having states updated by clock tokens.

3. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input; and

wherein converting one or more converted asynchronous circuit inputs having synchronous and asynchronous inputs comprises sampling the asynchronous inputs at the synchronous input clock rate.

4. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input; and

validating the converted asynchronous circuit design's timing against the synchronous circuit.

5. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous outputs at a circuit boundary to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output; and

the asynchronous output sending a confirmation of received data to the coupled asynchronous circuit logic.

6. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous outputs at a circuit boundary to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output; and

the asynchronous output sending a confirmation of received data to the coupled asynchronous circuit logic wherein the confirmation comprises lowering an enable line state indicating that an input from the asynchronous circuit logic is received in the asynchronous output.

7. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous outputs at a circuit boundary to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output;

the asynchronous output sending a confirmation of received data to the coupled asynchronous circuit logic wherein the confirmation comprises lowering an enable line state indicating that an input from the asynchronous circuit logic is received in the asynchronous output; and

resetting the asynchronous circuit input provided to the asynchronous output upon observing the enable line in a low state.

8. A method of converting a synchronous circuit to an asynchronous circuit, comprising:

converting synchronous circuit logic to an asynchronous circuit logic;

converting one or more asynchronous outputs at a circuit boundary to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output; and

the asynchronous output sending a confirmation of received data to the coupled asynchronous circuit logic wherein the asynchronous circuit logic comprises a field programmable gate array.

9. An integrated circuit, comprising

asynchronous circuit logic converted from a synchronous logic circuit; and

one or more asynchronous inputs at a circuit boundary of the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input;

wherein at least one of the one or more asynchronous inputs comprises an asynchronous circuit input having synchronous and asynchronous inputs that is operable to sample the asynchronous inputs at the synchronous input clock rate.

10. An integrated circuit comprising:

asynchronous circuit logic converted from a synchronous circuit design; and

one or more asynchronous outputs at a circuit boundary of the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output;

the asynchronous output further operable to send a confirmation of received data to the coupled asynchronous circuit logic comprising lowering an enable line state indicating that an input from the asynchronous circuit logic is received in the asynchronous output.

11. A machine-readable medium with instructions stored thereon, the instructions when executed operable to cause a computerized system to:

convert synchronous circuit logic to an asynchronous circuit logic; and

convert one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input;

wherein converting one or more asynchronous inputs comprises converting at least one asynchronous circuit input having synchronous and asynchronous inputs that is operable to sample the asynchronous inputs at the synchronous input clock rate.

12. A machine-readable medium with instructions stored thereon, the instructions when executed operable to cause a computerized system to:

convert synchronous circuit logic to an asynchronous circuit logic; and

convert one or more asynchronous outputs at a circuit boundary to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output;

wherein converting one or more asynchronous outputs comprises converting at least one asynchronous output to send a confirmation of received data to the coupled asynchronous circuit logic, the confirmation comprising lowering an enable line state indicating that an input from the asynchronous circuit logic is received in the asynchronous output.